The training, the internship and finally, the tape-out – VSD Silicon proven model
A dream and a mission statement that was framed 10 years back by VSD and efabless (or let us say, e-fabulous) has now taken a […]
Tag Archives: opensource EDA
Continue reading
‘vsdflow’ on CentOS is ready
to build the shell script for ‘vsdflow’ on CentOS, and finally I have the first cut ready. You just need to follow steps given in below link for CentOS, and all opensource EDA tools (PNR, STA, Layout, LVS) will be installed on your system. There are 2 testcases (picorv32 and spi_slave) inside the below link to test whether all tools have been installed or not. After running the shell script in below link, you need run the testcase
How about benchmarking Opensource openSTA against ——?
So, I took up two STA tools, OpenSTA from openroad project and “——-” from “——-“, to explain, to some extent, what “bench-marking” means to me. I would also encourage everyone reading this blog to come up with their definitions of “bench-marks” for other tools and we can model that. You can fill-up “——” with one of your favorite industry grade EDA tools. The concept of benchmark won’t change
Think about pre-placed cells and power ring generation in opensource EDA
Hey There – Think about it!! Today’s version of open-source EDA tools, work very well for hierarchical designs sub-25k instance count. For hierarchical designs ~500k […]
Re-define pad placement using open-source EDA
Hey There – Think about it!!! Last week, we shared our idea and vision of “How to define the width and height of core and […]
RISC-V Workshop @IIT Madras – Day 1
A keynote from Rick O’ Connor, executive director, RISC-V foundation, and we remember this to core of our heart, because of the below statement he made – “RISC-v is present in 27 countries and can be used by 57 % of population of World soon” That’s the spread of open-source ISA
A prestigious day for us…It can be for you..
A proud moment for our company VLSI System Design Corporation Pvt. Ltd., for my colleague Anagha Ghosh and for myself (See image below)
Our company’s first paper on IEEE explore for technology mediated learning – World’s prestigious institute for engineering and technology innovation. Here’s the link for the paper
https://www.vlsisystemdesign.com/vsdlibrary/
What is set_multi_cpu_usage in physical design or STA?
Do you want to find your answers too? Enroll in the upcoming webinar on “Distributed timing analysis” with Tsung-Wei, do labs on your own, understand the framework and I can guarantee you would be a better STA engineer or Lead than you were before 26th May.
Use this tool for PNR – Its FREE
If you learn this tool and use it to build your own applications, you might end up presenting a paper in our online conference happening soon called “VSDOpen” – The first ever online conference on opensource EDA.
