Symposium I – Front-end open-source EDA tool flows for IC design and verification

This blog is regarding abstract submission for VSDOpen2018, which is the first online conference in VLSI, that covers all aspects of semiconductor technology with prime focus to build SoC using RISC-V CPU by illustrating exciting ways using (only) opensource EDA tools.

This conference has 6 symposium, out of which first symposia is to come up with front-end EDA tool flows for IC design and verification. List of other symposium and session chair can be found in below link:

https://www.vlsisystemdesign.com/vsdopen2018-2/

This blog is about Symposium I – Front-end open-source EDA tool flows for IC design and verification (abstract submission last date is 15th August, please see above link for details)

Let’s see how you can implement a pipe-line in transaction-level verilog using Makerchip IDE, which is primarily the mode of implementation for this Symposium

Pipeline:
Pipeline is analogous to assembly plant, where we divide the processing work into stages, as you saw with RISC-V micro architecture (read this blog for more details). Let’s take an example of a logic which is computing Pythagoras theorem. The below code is the logic that is computing Pythagoras’s theorem. It’s computing the distance ‘c’ as square root of (a^2 + b^2)

And its equivalent transaction-level verilog is shown in the box in above image

The reason to $aa and not $a is just that the signal names in TL-verilog needs to be 2 characters, and not 1. There is an expression here for each bit of logic diagram shown below the code box (in above image). The “^2” represents a ‘square’ logic, a “+” represents ‘add’ logic and “sqrt” represents ‘square root’ logic. So in below expression, $aa_sq[31:0] = $aa ** $aa is square(a). Rest code should be self-explanatory

Next, we will copy paste the code in makerchip IDE and compile. We are doing this for the logic diagram, which is auto generated from Makerchip IDE. This is how the logic diagram looks like:

The above logic diagram matches the below in many ways. In TL-verilog, it uses an expression of logic, which is referred to as timing abstract. In RTL, we tend to have the mental picture of our design as shown under RTL tab in below image. And in TL-verilog, we tend to have a mental picture shown below the tab Timing-abstract in below image

In above image, under timing-abstract, we give ourselves a context of a pipeline and the pipeline is going to have stages 1, 2, 3. We are going to bucket our logic into those pipeline stages. Here, we are not bothering to draw flip-flops, explicitly. With this timing-abstract model, we don’t have to do that. Flip-flops are implied by the fact that I am drawing a wire from stage 1 to stage 2. The wire (perpendicular to vertical dashed line between stage 1 and 2) is a ‘$’ signal names, referred to as a pipe signal, which we have been using in TL-verilog and that pipe signal represent the signal assigned as well as all staged version of the signal

As depicted, lets give the above Pythagoras code, a context of pipeline using TL-verilog (And you will see how easy it is). Here’s the code:

\TLV

|calc

@1

$aa_sq[31:0] = $aa * $aa;

$bb_sq[31:0] = $bb * $bb;

@2

$cc_sq[31:0] = $aa+sq + $bb_sq;

@3

$cc[31:0] = sqrt($cc_sq);

\SV

endmodule

Once you compile the above code and investigate the logic diagram, you will see how beautifully makerchip has moved logics to different stages:

Now comes the magical part – the pipeline that we just created, below image shows the pipeline in TL-verilog (the one which we created above) and its corresponding verilog is on the right where you got explicit signal declarations for each of the individual wires, explicit flip-flops and the assignment statements.

Question – Who doesn’t want a 3.5X improvement in their code size? I guess everyone wants efficient and effective improvement. Now these are just few tips to have the easy implementation of pipe-line. You are free to implement your ideas in TL-verilog, compile, simulate and see the improvements on your own. For few more tips, you might want to check out below course on “VSD – Pipelining RISC-
V with TL-verilog”

https://www.udemy.com/vsd-pipelining-risc-v-with-transaction-level-verilog/

All your ideas will be reviewed by below panel of session chairs (who are all experts in their domains) and you might just get a chance to showcase your innovation to top crowd from VLSI industries:

The reason for this conference is to do out-of-the-box things in field of VLSI, to showcase your versatility and talent to a lot of TOP people, and get their attention, all online.

“This can be your new creative resume”

All the best for your submissions and happy learning

Registration for Ethical RISC-V IoT Workshop

Welcome to Ethical RISC-V IoT Workshop

The “Ethical RISC-V IoT Workshop” at IIIT Bangalore, organized in collaboration with VSD, is a structured, educational competition aimed at exploring real-world challenges in IoT and embedded systems. Participants progress through three stages: building an application, injecting and managing faults, and enhancing application security. The event spans from May 9 to June 15, 2024, culminating in a showcase of top innovations and an award ceremony. This hands-on hackathon emphasizes learning, testing, and securing applications in a collaborative and competitive environment.

Rules :
  1. Only for Indian Student whose college is registered under VTU
  2. Only team of 2 members can Register
  3. Use only VSDSquadron Mini resources for product development
Awards :
  1. Prize money for final 10 Team
  2. 3 Winner team’s Product will be evaluated for Incubation
  3. 7 consolation prizes
  4. Completion Certificate to final round qualifier
  5. Chance to build a Proud Secured RISC-V Platform for India

Date for Registration : 9th May - 22nd May, 2024
Hackathon Inauguration : 23rd May 2024

VSDSquadron (Educational Board)

VSDSquadron, a cutting-edge development board based on the RISC-V architecture that is fully open-source. This board presents an exceptional opportunity for individuals to learn about RISC-V and VLSI chip design utilizing only open-source tools, starting from the RTL and extending all the way to the GDSII. The possibilities for learning and advancement with this technology are limitless.

Furthermore, the RISC-V chips on these boards should be open for VLSI chip design learning, allowing you to explore PNR, standard cells, and layout design. And guess what? vsdsquadron is the perfect solution for all your needs! With its comprehensive documentation and scalable labs, thousands of students can learn and grow together.

VSD HDP (Hardware Design Program) Duration-10 Week

With VSD Hardware Design Program (VSD-HDP),  you have the opportunity to push the boundaries of what exist in open source and establish the new benchmark for tomorrow.

It will leverage your degree in Electrical or Computer Engineering to work with

  • Programmable logic
  • Analog/ digital IP
  • RISC-V
  • Architecture & microprocessors
  • ASICs and SoCs on high-density digital or RF circuit cards
  • Gain hands-on knowledge during design validation and system integration.

Sounds exciting to just get started with expert mentors, doesn’t it? But we are looking for the next generation of learners, inventors, rebels, risk takers, and pioneers.

“Spend your summer working in the future !!”

Outcomes of VSD Online Research IP Design Internship Program

  1. Job opportunities in Semiconductor Industry
  2. Research work can be submitted to VLSI International journals
  3. Participate in Semiconductor International Conference with Internship Research Work
  4. Paper Publications in IEEE Conference and SIG groups
  5. Tape out opportunity and IP Royalty
  6. Interact with world class Semiconductor designer and researchers
  7. Academic professions where more research projects are encouraged.
  8. All the above research and publication work will help colleges and institutes to improve accreditation levels.

Know More Information

VSD – Intelligent Assessment Technology (VSD-IAT)

VSD – Intelligent Assessment Technology (VSD-IAT) is expertly built training platform and is suited for designer requirements. Semiconductor companies understand the value of training automation and Engineer performance enhancement, and do not need to be convinced of the impact of a virtual platform for learning. VSD trainings are quick, relevant, and easy to access from any device at any time zone.

VSD Intern Webinars

VSD Interns made it happen !!

VSD is working towards creating innovative talent pool who are ready to develop design and products for the new tech world. VSD believes in “Learning by doing principle” , and always prepare the student to apply the knowledge learned in the workshops, webinars and courses. We always push our students to work on new designs, test it and work continuously till it becomes the best performing design. Any student who enrolls to VSD community starts working with small design and grows with us and develops a tapeout level design with complete honesty and dedication towards the Work !!

Check out VSD Interns Achievement!

VSDOpen Online Conference

Welcome to the World’s only online conference in Semiconductor Industry VSDOpen Conference. With enormous support and global presence of audience from different segments of industrial lobby and academia made a highly successful event. Evolution is change in the genetic makeup of a population over time, online conference is one kind evaluation everyone adapt soon. 

  • VSDOpen 2022 is an online conference to share open-source research with the community and promote  hardware design mostly done by the student community.
  • VSDOpen 2022 is based on the theme “How to lower the cost to learn, build, and tapeout chips ?”  , which will provide a platform to community to build stronger designs and strengthen the future of Chip design.
  • VSDOpen is envisioned to create a community based revolution in semiconductor hardware technology.
  • The open source attitude is required to bring out the talent and innovation from the community who are in remote part of world and have least access to the technologies.  And now Google support will help to bring the vision to execution by VSD team

VSD Online Course by Kunal Ghosh

VSD offers online course in complete spectrum of vlsi backend flow from RTL design, synthesis and Verification, SoC planning and design, Sign-off analysis, IP Design, CAD/EDA automation and basic UNIX/IT, Introduction to latest technology – RISC-V, Machine intelligence in EDA/CAD, VLSI Interview FAQ’s.

Current Reach – As of 2021, VSD and its partners have released 41 online VLSI courses and was successfully able to teach  ~35900 Unique students around 151 countries in 47 different languages, through its unique info-graphical and technology mediated learning methods.

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