4th mile-stone – 35 RISC-V cores in 5-days – Can you believe it?

No? No problem – We will share GitHub links also this time to show what’s possible in 5-days

Yes – We did it again, in much bigger and better way
Last time, when we did a 5-day RISC-V workshop and @Steve claimed that you can achieve a basic RISC-V core in 5-days, there were a lot of apprehensions and strong oppositions/doubts about the credibility of this workshop. I am really Thankful to all critics as that helps improve the quality and intensity of the upcoming workshop.

This time, we decided, let’s build an automated infrastructure where participants can check-in each line of their code. Thanks to @Shivam for his amazing idea of configuring Classroom GitHub. And that’s it. We had Makerchip IDE, TL-Verilog, Day wise Slack channels, Classroom GitHub and VSD-IAT – All of them so seamlessly integrated that every participant followed the loop and there you go. Out of 110 participants, 35 participants built entire basic RISC-V CPU core which is close to 30% participants, and all in 5-days

Thanks to @Steve for his amazing Makerchip IDE and TL-Verilog which makes coding RISC-V CPU so simple. Now we are convinced about the format of the VSD workshops where participants passionately work for 14hrs per day and don’t even get tired. In-fact, they ask for more. That’s an amazing response. Look at the images below, and we will also release GitHub Links very soon on our website.

Finally, Thanks Gautham Pai for his amazing Jnaapti Platform and 24/7 support. He is equally passionate about VSD workshops. To all my senior and experienced friends in industry – Let’s again take a back seat and encourage all participants by congratulating them. They are the future torch-bearers of open-source and RISC-V

Read below blog for more details:

Posted in Concepts, Design, IP design, Open Source, RISC-V, Tool related.

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