Paper 2: PNR for digital core IC to pads using Cloud based eda tool

Anand Rajgopalan Completed bachelor’s in Electrnics & Telecomm Enginnering from Mumbai University. Microelectronics was my elective subject in one of the semesters. Design & Synthesis of Real time clock in Altera CPLD board . Presently I have took training from VLSI Guru, Bangalore  in Functional Verilog , did some projects based on AXI protocol and memory verification

Posted in Concepts, Conference, Design, Floorplan, VSDOpen 2018 Conference papers.

Leave a Reply

Your email address will not be published. Required fields are marked *