Paper 6: Formally Verifying WARP-V, an Open-Source TL-Verilog RISC-V Core Generator

Akos Hadnagy is a master’s student at TU Delft. He became involved in the WARP-V project through the Google Summer of Code programme this summer. His interest includes heterogeneous and reconfigurable computing, FPGA and hardware development.


Posted in Concepts, Conference, Design, RISC-V, VSDOpen 2018 Conference papers.

Leave a Reply

Your email address will not be published. Required fields are marked *