VSD – IIIT Bangalore – Unique example of industry-academia collaboration – 12 chip tapeouts in 2 months

Two months ago, VSD and IIIT Bangalore entered into an informal industry-academia engagement. In this engagement, VSD is supposed to take an ASIC course for IIIT Bangalore under-grads and post-grads. The engagement started in a very smooth manner, where VSD was given complete flexibility to decide on a full 6-month semester curriculum. Thanks to Prof. Madhav Rao and Prof. Nanditha Rao for helping in all possible ways within their reach to start this course with an external industry at such a fast pace
Result - Yesterday, 12 out of 60 (20%) students submitted their designs for tapeout, which is amazing because the students were introduced to ASIC flow just two months back.
I am so thankful to IIIT Bangalore which took the risk that helped VSD-IIIT Bangalore to set a unique industry-academia model for all colleges across India regarding how tapeout-oriented ASIC design courses can be a part of a full semester curriculum, given the amount of flexibility for curriculum change and mapping to latest industry needs. And thanks to Google/Skywater/efabless for opening up the foundry information, due to which we were able to provide chip design and manufacturing experience to a whole cohort

Moreover, the entire engagement was on the VSD-IAT EdTech platform for chip design, which makes the model more scalable, which means, that while IIIT Bangalore students were taping out their designs, VSD was engaged with another cohort to build IPs on the cloud for an upcoming hackathon with FOSSEE team, IIT Bombay and was also engaged in cloud-based nationwide Verification hackathon with NIELIT and IIT Madras


Exciting times and exciting opportunities are here for all colleges. Take a look at the designs in the below link
Now looking forward to more medium-complexity SoCs. Stay tuned
All the best and happy learning !!
Posted in Concepts, Design, Google/SKywater130, Open Source, RISC-V, Tapeout, VSD-Hardware Design Program.

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