AI and machine learning (branch of AI) needs deep neural networks, which in turn requires high-performance computing. SiFive and RISC-V organization were happy to announce a solution, tailored to this requirement to AI/ML start-ups in Bangalore on 23rd August
That’s exactly what happened in DAC2018 at Moscone Center, San Francisco. I was invited for a talk in DAC summer school, on my work “vsdflow” which is also one of the main topics of discussion in my “TCL programming” course on Udemy. I would say, the entire DAC was a journey of events, exchange of ideas between brightest minds of the world.
Symposium V – Machine Intelligence in EDA/CAD applications- Let’s investigate a simple Wire Resistance Estimate (WiRE) model
This is common design automation problem which is used for estimating timing and power characteristics for analysis and implementation for many steps in ASIC flow. We will restrict our scope to physical implementation only, where known quantity is “length” of wire and resistance is predicted.
Last week we conducted Machine Learning contest where participants were asked to modify loss function program to bring out best possible accuracy in terms of mean and sigma, by designing a new multinomial model. We have a winner and a special mention
let’s identify what has happened till date in field of EDA/CAD using Machine intelligence. The image below shows the flow diagram for designing a chip. This is what has happened (or happening) in EDA using machine intelligence.
This webinar will talk about how do you do that using Machine Learning and Deep Learning techniques. Participants for this webinar range from students to some of service company India head and Program managers. So we will cover from basics to advanced + labs on cloud.
Webinar presents a hands-on approach with session on GPUs, solving design automation problems with modern machine intelligence techniques by including step-by-step development of commercial grade applications including resistance estimation, capacitance estimation, cell classification and others using dataset extracted from designs at 20nm.