Paper 6: Formally Verifying WARP-V, an Open-Source TL-Verilog RISC-V Core Generator

This paper introduces TL-V erilog and W ARP-V and then describes the formal verification of WARP-V using riscv-formal, a formal verification framework for RISC-V. Timing-abstraction and transaction-level design are showing significant benefits for hardware modeling, but this is the first demonstration of their benefits for verification modeling. As evidence of these benefits, the verification of all RISC-V configurations of WARP-V is accomplished in a single page of code.

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Paper 5: Introduction to TL-Ver & Front-End Symposium

Steve Hoover is the founder of Redwood EDA. Steve holds a BS in electrical engineering from Rensselaer Polytechnic Institute and an MS in computer science from the University of Illinois. He has designed numerous components for high-performance server CPUs and network architectures for DEC, Compaq, and Intel. Students will learn Transaction-Level Verilog modelingtechniques to generate Verilog models in half the time using the makerchip.comfree online IDE. A new open-source RISC-V CPU development effort will be introduced that showcases flexible IP design practices.

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Symposium I – Front-end open-source EDA tool flows for IC design and verification

Question – Who doesn’t want a 3.5X improvement in their code size? I guess everyone wants efficient and effective improvement. Now these are just few tips to have the easy implementation of pipe-line. You are free to implement your ideas in TL-verilog, compile, simulate and see the improvements on your own. For few more tips, you might want to check out below course on “VSD – Pipelining RISC-
V with TL-verilog”

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On-Chip Variation (OCV) – Part 4

Hello And, finally, we have a video on what we posted on this topic. Below is the snippet of the same. Full video can be found under Section 20 on VLSI Academy Course Some prefer reading, some prefer moving images…. Luckily, we have both :). Get back to me in case you […]

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On-Chip Variation (OCV) – Part 3

Hello, The below image models “low-to-high waveform condition” at input of CMOS inverter, in terms of resistances and capacitance. So, overall, its the RC time constant that actually decides the delay of a cell With above, we can safely say, the propagation delay tPD is a function of ‘R’ Now, […]

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On-Chip Variation (OCV) – Part 2

Hello Today, I was a guest speaker at one of the biggest Technical Conference held in Bangalore, and luckily I met few people who had read my previous post. This is what I call “From Virtuality to Reality“. Its really awesome feeling, when you get to meet people personally. We […]

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On-Chip Variation (OCV) – Part 1

Hello Ever thought what’s an interviewer’s favorite questions to rip you off – all of my previous post :). And On-Chip Variation (OCV) is one of them, specifically for Static Timing Analysis interview. This analysis is coming from people who got interviewed and recruited into leading VLSI industries. Most importantly, […]

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