Switching threshold – Clock buffer : The relationship starts here
Hello – In my last post, I was very happy about the robustness of CMOS logic. And here’s more reason to be happy to discover what […]
Author Archive: Kunal
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That’s why I love CMOS logic!
Hello It’s so robust… I can give you 4 instances of this 1) Vary PMOS width size to its maximum, keeping NMOS width constant and […]
Power aware clock tree synthesis – Part 4
Hello We were looking for a solution for below scenario, and you will be amazed to see, how an ‘Universal Gate’ solves the below problem […]
Power aware clock tree synthesis – Part 3
Hello And here’s the solution to the problem posted in my previous article. ‘AND gate itself’. If you observe carefully, you tie one of the […]
Power aware clock tree synthesis – Part 2
Hello While trying to build a clock tree which is power aware, let’s go back a step ahead and look, what are the top observations […]
Power aware clock tree synthesis – Part 1
Hello How about saving some power for the below clock tree network ? It’s tricky and if we go with the right approach, we might […]
CMOS VTC – Believe it or not – You use it ‘daily’ – Part 4
Hello Long time … since my last post …. Reason : Hopefully, I have given enough time for you to get hold on my previous […]
CMOS VTC – Believe it or not – You use it ‘daily’ – Part 3
Hello If you have read through my previous posts on the above topic, things have seriously become interesting over here. I mean, isn’t that exciting, […]
CMOS VTC – Believe it or not – You use it ‘daily’ – Part 2
Hello I will derive the CMOS VTC in few steps, and below is the first one. We did derive the below equations sometime back, and […]
CMOS VTC – Believe it or not – You use it ‘daily’ – Part 1
Hello So you are aware of the below image? No…. Well, this is CMOS – Voltage Transfer Characteristics curve and you use it almost daily. How? […]
