Timing libraries – This is where body and soul meets…!!
Get geared up for my next “to be” launched course on CCS timing libraries – Constructs and characterization. Let me be a bit frank here […]
Author Archive: Kunal
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“20ps < clock_tran < 60ps”, ever wondered what’s the real reason?
I am sure you must have…. This blog will just walk you through the reasons using cool images from my latest course on “Static Timing […]
Latch timing – Beg, borrow or steal !!
Sounds crude … This is how it functions. Well, in my opinion, it’s not as crude as it sounds, but a very smart way to […]
Myself, Reset Synchronizer – I synchronize the asynchronous
Hi Everyone, My name is ‘Reset Synchronizer’. I have been tasked to do a very specific job. Though, I look to be a very small […]
Ever seen a blended video blog on interface timing analysis – here’s one for you!!
I have seen blogs on interface analysis, they are awesomely written out. But one thing that I find missing in them is how it works […]
World celebrates its 2017th year and we celebrate our 6th…
I would like to “Thank You” for being a part of our community of 10500+ people since 2011, all with a same mission – high […]
A video blog on latch based clock gating and integrated clock gate cell
Hello There’s nothing much to be written about in this blog as this is a video blog. Look at below video which is a sample […]
Latch based clock gating – clock gating analysis revisited
Hello In my last blog, which received huge response, I talked a simple and efficient technique for clock gating. But it came with an additional […]
Clock gating analysis – why, what, how?
Hello Now let me first be very clear – This blog is for freshers in static timing analysis domain. This topic had been very confusing […]
The curious case of ‘interface analysis’!!
Hello This is an important part of static timing analysis, Below is the link: https://www.udemy.com/vlsi-academy-sta-checks-2 I would love to talk about it a lot in […]
