So you are aware of the below image? No….
Well, this is CMOS – Voltage Transfer Characteristics curve and you use it almost daily. How? The sharpness of this curve decides how fast your cell phone is…. basically, it is used to calculate the delay of any logic gate. Stay with me and I will show you how…..
With that introduction, let me first show you (and most of you might already know), the above curve is derived (using well defined steps) from NMOS/PMOS Id-Vd curves.
Now, is that surprising? Well, ‘yes’ and ‘no’. Why ‘no’? Because, CMOS is built using NMOS/PMOS, so obviously, it will have connection with their characteristics
Why ‘yes’? Because, what I have showed you, till now, through my videos or posts, is the, NMOS/PMOS drain current (Id) and drain voltage (Vds) characteristics based on constant gate-voltage (Vgs), but the above curve is completely dependent on ‘Vin’ and ‘Vout’
That’s the catch!!! There should be some way to convert ‘Vds’ and ‘Vgs’ as function of ‘Vin’ and ‘Vout’
Let’s start with basic NMOS/PMOS curves, which I believe can easily be derived using SPICE simulations. Below image also shows the relationship between different ‘transistor’ level voltages (i.e. Vds, Vgs) and ‘logic gate’ level voltages (i.e. Vin, Vout)
In a real world, it does makes sense to have curves which are dependent on ‘Vin’ and ‘Vout’ rather than device level voltages ‘Vds’ and ‘Vgs’, as most of your PNR tools deals with slew values which are highly dependent on ‘vin’ and ‘vout’. They decide the voltage swing
With that background, I will show you (using the above image as reference), how do we derive the CMOS VTC in just few and easy steps.
“Take the broken pieces of your life, bake a master cake out of it“ – ― Israelmore Ayivor, Dream Big!: See Your Bigger Picture!
And that’s what we will do for this topic. Stay Tuned