our company to move from LMS (Learning Management System) to EMS (EDA Management System), and finally we envision, very soon to be in DMS (Design Management System).Talking about ‘vsdflow’, it’s the main theme of this paper, and if I had to describe it in few lines, it’s a ‘plug and play (PnP)’ EDA management system, built for chip designers to implement their ideas and convert to GDSII.
read_sdc is been considered as a very critical command in EDA world, as this is the command which defines your specifications, and if not written and interpreted correctly, can lead a huge delay in tapeout cycle.
You see how every sentence in the title is connected!!! As you are aware about the big launch on “CCS Library” course, I just wanted […]
Get geared up for my next “to be” launched course on CCS timing libraries – Constructs and characterization. Let me be a bit frank here […]
Hello It’s so robust… I can give you 4 instances of this 1) Vary PMOS width size to its maximum, keeping NMOS width constant and […]
Hello Long time … since my last post …. Reason : Hopefully, I have given enough time for you to get hold on my previous […]
Hello If you have read through my previous posts on the above topic, things have seriously become interesting over here. I mean, isn’t that exciting, […]
Hello I will derive the CMOS VTC in few steps, and below is the first one. We did derive the below equations sometime back, and […]
Hello So you are aware of the below image? No…. Well, this is CMOS – Voltage Transfer Characteristics curve and you use it almost daily. How? […]
Hello After my last post on “Regular buffer v/s Clock buffer – Part 2“, I received several mails on having a video of the post. […]