This paper describe a rapid backend process flow (synthesis, placement, STA, routing) and top level integration to implement a small RTL IP into a tapeout ready chip using the Efabless online platform . The full process is completed in less than 3 hours. The IP implemented is a configurable frequency divider
Design Verification is critical to proving functional correct- ness and establishing confidence in a design. Several stud- ies from industry and academia, particularly over the course of the last two decades, have explored various verifica- tion methodologies that fall somewhere between dynamic or purely static formal approaches.
System-on-Chips (SoCs) today have become extremely complex structures housing heavily optimized cores, count- less peripherals, and large interconnect fabrics. Even re- stricting ourselves to just verifying the microprocessor, the state space to be verified is enormous and cannot be exhaus- tively explored in any finite amount of time. Manually writ- ten tests, while effective at capturing some complexities of design intent, suffer from the fact that they are expensive in cost and time required to develop them. Random stimulus methods perform better because they eventually cover many cases. Most new ideas in dynamic verification over the last two decades have largely been towards semi formal verifi- cation methodologies such as coverage driven verification and constrained test generation. In this paper, we explore an approach to dynamic functional verification that we use at the RISE lab, IIT Madras for the verification of the RISC-V based Shakti cores.
A simple chip frequency divider but most prominently used in counter modules of a microproceesor or as standalone IC can be completely designed from Verilog code to layout . A complete chip with IO pins and labels on it can be designed with help of efabless cloud based eda tool just like a commercial IC. There are two toolbox in efabless one is CloudV for Verilog or c code & other is Open Galaxy for backend design for designing commercial like IC with zero cost involved & same can be given to Semiconductor foundries for mass production. From Preparation , synthesis to DRC cleanup using Q flow manager a Core part of IC can be obtained with log files of each stage used in this process. A innovative feature of interactive DRC under Magic tool enables the designer to rectify DRC violations on the spot. Moreover, ESD protection is also available under Opengalaxy tool for use of chip in electrosensitive applications.
Mohamed Kassem is the CTO and Co-Founder of efabless.com, the first semiconductor company applying open community innovation to all aspects of product development. Prior to launching efablesshe […]
An opensource padframe generator was developed on the efabless platform for usage with the Open-Source Qflow Digital Synthesis Flow, for digital logic chips in the X-FAB XH018, 180nm process.
Timing-driven optimization is imperative for the success of closure flows. The optimization engine applies changes to the design and estimates circuit delays quickly and accurately to improve timing, area, and power performance. This procedure is inherently complex and computationally challenging.
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VSDOpen 2018 Keynote 1 : A New Golden Age for Computer Architecture: History, Challenges, and Opportunities
A New Golden Age for Computer Architecture: History, Challenges, and Opportunities, David Patterson, UC Berkeley and Google, October 26, 2018Full Turing Lecture: https://www.acm.org/hennessy-patterson-turing-lecture
Welcome to first ever online semiconductor technology conference with prime focus to build SoC using RISC-V CPU using Open-source EDA tool on 27th October 2018, 8:00 AM to 3:00 PM
Free registration for IITM Participants:
Online viewing Zoom link will be send 12 hours in advance.
Alternatively, IITM view point: A.M. Turing Hall (BSB 361)
Please register using the form below, its on first come first serve basis.
Contact us at 8548037643 or firstname.lastname@example.org
Design Verification is critical to proving functional correctness and establishing confidence in a design. Several studies from industry and academia, particularly over the course of the last two decades, have explored various verification methodologies that fall somewhere between dynamic or purely static formal approaches.
Random stimulus methods perform better because they eventually cover many cases. Most new ideas in dynamic verification over the last two decades have largely been towards semi formal verification methodologies such as coverage driven verification and constrained test generation. In this paper, we explore an approach to dynamic functional verification that we use at the RISE lab, IIT Madras for the verification of the RISC-V based Shakti cores.