Tag Archives: Steve Hoover

13-Year-Old, Nicholas Sharkey, Creates a RISC-V Core

It was also a real testament to Nicholas’s thirst for knowledge and the outside-the-box thinking of his home-schooling parents, Rasa and Mike. Having a 13-year-old of my own, I was particularly impressed by Nicholas’s willingness to put himself out there, asking questions and joining Zoom calls (not to mention his familiarity with Linux). I’ve since learned that Nicholas has been awarded in spelling bees and math competitions and is an expert at solving the Rubik’s Cube. Somehow, I’m not surprised.

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150+ students have decided to upskill in VLSI

And that’s where VSD must play an especially important role to bring in latest and greatest VLSI skills to you, atleast in the field of open-source hardware. VSD owes a lot to VLSI community and hence has planned 3 exclusive cloud lab-based VLSI workshops on 3 important topics, with top 3 expert instructors from around globe,  having more than 2 decades of experience – Tim Edwards, Steve Hoover, and Prof. Mohamed Shalan

Open-source EDA tool development with lab exercises using Sky130 pdk’s by Google/Skywater
RISC-V micro-architecture using transaction level – Verilog with lab exercises on Makerchip Platform
SoC and Physical Design using Automated RTL2GDS OpenLANE tool with lab exercises using demo design and Sky130 pdk’s.

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From VLSI to System Design (SoC) – The choice of SPI

SPI model is a master/slave model. There’s some SPI master which determines who gets to transmit and who gets to receive. The output from SPI master is called MOSI (Master Out Slave In). If you have 2 slaves, slave 1 and slave 2, as shown below, MOSI goes to all the slaves .Then you have another line MISO (Master In Slave Out). All the wires are connected, as shown in below image. Then you have a master only function called SCLK, which goes to all the slaves. Now also, there must be a slave select (SS) for S1 and a slave select for S2.

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