to build the shell script for ‘vsdflow’ on CentOS, and finally I have the first cut ready. You just need to follow steps given in below link for CentOS, and all opensource EDA tools (PNR, STA, Layout, LVS) will be installed on your system. There are 2 testcases (picorv32 and spi_slave) inside the below link to test whether all tools have been installed or not. After running the shell script in below link, you need run the testcase
This paper describe a rapid backend process flow (synthesis, placement, STA, routing) and top level integration to implement a small RTL IP into a tapeout ready chip using the Efabless online platform . The full process is completed in less than 3 hours. The IP implemented is a configurable frequency divider
A simple chip frequency divider but most prominently used in counter modules of a microproceesor or as standalone IC can be completely designed from Verilog code to layout . A complete chip with IO pins and labels on it can be designed with help of efabless cloud based eda tool just like a commercial IC. There are two toolbox in efabless one is CloudV for Verilog or c code & other is Open Galaxy for backend design for designing commercial like IC with zero cost involved & same can be given to Semiconductor foundries for mass production. From Preparation , synthesis to DRC cleanup using Q flow manager a Core part of IC can be obtained with log files of each stage used in this process. A innovative feature of interactive DRC under Magic tool enables the designer to rectify DRC violations on the spot. Moreover, ESD protection is also available under Opengalaxy tool for use of chip in electrosensitive applications.
So glad and happy to let you know that we will be presenting in RISC-V workshop at IIT Madras, India, on July 19, 2018 at 2pm (organized by RISC-V foundation), and topic is something which we have mastered in last 7 years – its about a survey of E31 RISC-V core floorplan and its impact on power, performance and area.
A working chip is all using opensource EDA tools (no more license fee). Of course, its taped-out in 180nm technology. But who knows, this might be just the beginning. Upcoming blogs will talk more about the commercial angle of this. Let’s see how it is going to benefit student/professionals/innovators community
Well, that’s was just a demo of the powerful efabless platform. Do you want to know more about this powerful yet simple platform? Do you want to build complete SoC using this platform? We did an entire webinar on this, and here’s the copy of it.