Chennai, we are coming to you for next RISC-V workshop…

Hey There,

So glad and happy to let you know that we will be presenting in RISC-V workshop at IIT Madras, India, on July 19, 2018 at 2pm (organized by RISC-V foundation), and topic is something which we have mastered in last 7 years – its about a survey of E31 RISC-V core floorplan and its impact on power, performance and area.

Below are our badges

Here’s the direct link to our topic details which we will be presenting

https://tmt.knect365.com/risc-v-workshop-chennai/agenda/2#a-survey-of-e31-risc-v-core-floor-plan-and-its-impact-on-power-performance-and-area-ppa

I must say, this is a great opportunity for people staying around IIT Madras to catch-up with us and our team, as we have been just talking over emails and meeting you LIVE will be something which VSD team will be looking forward to.

If you are a college student, you should receive some cool discounts for RISC-V workshop registration, and you might browse around above link for details about registrations. This is a 2-day workshop on July 18 – July 19, and you might as well get a chance to meet innovators of this latest technology

Coming to RISC-V, if you really want to meet us and talk technical, I would suggest you go through below 4 courses, and let me assure you – having a certificate in this technology is something which you should be looking forward to, as this is the future. Not very far from now, you will see all devices, mobiles, laptops being run on this architecture.

As a knowledge base, refer to my 2 below basic courses on RISC-V ISA-

https://www.udemy.com/vsd-riscv-instruction-set-architecture-isa-part-1a/?couponCode=RISCV_WORKSHOP

https://www.udemy.com/vsd-riscv-instruction-set-architecture-isa-part-1b/?couponCode=RISCV_WORKSHOP

Not only that, take one more step ahead and if you are looking to build RISC-V SoC, I would say, below 2 courses cover almost all domains of chip design starting from SoC planning, verification (in brief), RTL synthesis, Physical design, physical verification, DRC, LVS and Tape-out.

SoC planning:

https://www.udemy.com/vsd-making-the-raven-chip-how-to-design-a-risc-v-soc/?couponCode=RISCV_WORKSHOP

SoC physical design:

https://www.udemy.com/vsd-soc-design-of-the-picorv32-riscv-micro-processor/?couponCode=RISCV_WORKSHOP

The chip which is being built in above 2 courses is something which is going to tape-out very soon. It’s an amazing experience to “tape-out online”. Never heard of it, right? Go ahead, learn online

Would be good, if you prepare above courses and come to IIT Madras for a quick chat, OR, you can generally come to venue, talk, meet and we will let you know our vision

Excited to present in workshop, just 10 days from now, and also excited to meet you soon…

All the best and happy learning….

Spread the word
Posted in Concepts.

Leave a Reply

Your email address will not be published. Required fields are marked *


This site uses Akismet to reduce spam. Learn how your comment data is processed.