Power rail discontinuity – We would like to have continuous power rail.N- and P-diffusion discontinuity – We would like to have continuous diffusion. For my Physical design friends, remember, we add “FILLER” cells at the end of routing, and you always wondered why we are doing so.Small substrate contacts – Except for inverter, all substrate contacts are single width, which will create high resistance path for current, thus increasing “Clk-to-Q” delay.Hanging metal1 – If you see for the NAND gate outputs, there is lot of hanging metal1.
our company to move from LMS (Learning Management System) to EMS (EDA Management System), and finally we envision, very soon to be in DMS (Design Management System).Talking about ‘vsdflow’, it’s the main theme of this paper, and if I had to describe it in few lines, it’s a ‘plug and play (PnP)’ EDA management system, built for chip designers to implement their ideas and convert to GDSII.
read_sdc is been considered as a very critical command in EDA world, as this is the command which defines your specifications, and if not written and interpreted correctly, can lead a huge delay in tapeout cycle.
Looks like a very popular EDA command, isn’t it? Yes, it is. Well, this command actually is just an interface for users. At the back-end, […]
Hello And you thought we are done with CPPR… No … not yet … We haven’t done the “Hold” analysis yet. Its simple, but its […]
Hello It’s been 5 days since my last post (and that was intentional). I wanted to go slow on this topic, as this is an […]
Hello Hope everyone had a good weekend :)! And the reason for this post is to help friends and people in my circle to crack […]
Hello Let me quote “Winston S Churchill”, who said “A pessimist sees the difficulty in every opportunity; an optimist sees the opportunity in every difficulty.” […]
Hello, This is in continuation to the previous post, where I explained about transistor level implementation of negative and positive latch. In this post, I […]
Hello, I have been receiving multiple queries on what is clk-to-q delay, how’s it different from library setup time and library hold time, etc. I […]