design rule check – looks complex, but easy to code..!!

…and that’s exactly the perception that I am determined to solve.

People in my physical design course have had a glimpse of design rule check (DRC) step as a part of physical design flow, where I had mentioned that I will get back to DRC concepts. Well, I did…. in my newly (pre)launched course on ‘Custom Layout’. Let me walk you through few snippets of how to code, verify and correct drc in a custom layout. The similar concept can be propagated towards complete chip layout

I will not use any ‘node’ specific rule so as to avoid any proprietary or legal issue (which, by the way, is more complex problem than drc, to solve :)), I will use ‘lambda’ based design rules. So lambda, as shown in below pic, can be formulated as L/2, where L is minimum feature size (any node).

Let’s look how to code a basic rule for polysilicon width. Here I create a table with ‘minimum width’, ‘design rule’ and ‘actual width’ columns. I will fill it with some values, first, then I will code it in tech file. Let’s take an example of minimum polysilicon width to be ‘2lambda’.

So, I will fill the 2nd and 3rd column as ‘2lambda’ and code it in tech file with something like below syntax

The syntax is easy to interpret…. it says, min width of poly is 2 (lambda is the units) and if min drawn width or actual width is less than 2, the error message “your poly width is < 2, so flagging DRC error” will be flagged.

This complete rule goes under the drc section of tech file something like below:

drc

width poly 2 \

“your poly width is < 2, so flagging DRC error ”

end

Now the interesting part.. when you load MAGIC layout tool (which is an open source tool I have been using to do practical layout examples in the course) with the tech file having the above drc rule coded, MAGIC tool will honor the rule, and if designer violates the rule, he will get an error message plus the area on layout for which the error is being flagged, like below:

 

If you look into right bottom in above image, you will notice that a small section of poly silicon layer violates the rule of 2lambda, which is coded in tech file (look into drc section highlighted in tech file on top left of above image). Now to identify for designer, that this is a violation, MAGIC tool helps you with an error white dots shown in cursor box in above layout bottom right. While keeping the cursor box over the area of violation, and typing the command ‘drc why’ in MAGIC console, shown in bottom left of above image, you will see the reason why its DRC violated. Its the same message that you coded in tech file

Isn’t that “FREEDOM” to code your own DRC rules and use them in your own layout tool? Now you have full control over your design and nothing can stop you from experimenting and innovating…and that’s exactly what I have covered in my course on custom layout….

Innovation happens when people are given the freedom to ask questions and the resources and power to find answers” — Richard Branson

Now you have everything you need…a FREE layout tool, a METHOD to code and learn your own drc rules, and an AWESOME COURSE which helps you explain how you do all of above….

So what the wait for!!!

Get in and INNOVATE!!!

Registration for Ethical RISC-V IoT Workshop

Welcome to Ethical RISC-V IoT Workshop

The “Ethical RISC-V IoT Workshop” at IIIT Bangalore, organized in collaboration with VSD, is a structured, educational competition aimed at exploring real-world challenges in IoT and embedded systems. Participants progress through three stages: building an application, injecting and managing faults, and enhancing application security. The event spans from May 9 to June 15, 2024, culminating in a showcase of top innovations and an award ceremony. This hands-on hackathon emphasizes learning, testing, and securing applications in a collaborative and competitive environment.

Rules :
  1. Only for Indian Student whose college is registered under VTU
  2. Only team of 2 members can Register
  3. Use only VSDSquadron Mini resources for product development
Awards :
  1. Prize money for final 10 Team
  2. 3 Winner team’s Product will be evaluated for Incubation
  3. 7 consolation prizes
  4. Completion Certificate to final round qualifier
  5. Chance to build a Proud Secured RISC-V Platform for India

Date for Registration : 9th May - 22nd May, 2024
Hackathon Inauguration : 23rd May 2024

VSDSquadron (Educational Board)

VSDSquadron, a cutting-edge development board based on the RISC-V architecture that is fully open-source. This board presents an exceptional opportunity for individuals to learn about RISC-V and VLSI chip design utilizing only open-source tools, starting from the RTL and extending all the way to the GDSII. The possibilities for learning and advancement with this technology are limitless.

Furthermore, the RISC-V chips on these boards should be open for VLSI chip design learning, allowing you to explore PNR, standard cells, and layout design. And guess what? vsdsquadron is the perfect solution for all your needs! With its comprehensive documentation and scalable labs, thousands of students can learn and grow together.

VSD HDP (Hardware Design Program) Duration-10 Week

With VSD Hardware Design Program (VSD-HDP),  you have the opportunity to push the boundaries of what exist in open source and establish the new benchmark for tomorrow.

It will leverage your degree in Electrical or Computer Engineering to work with

  • Programmable logic
  • Analog/ digital IP
  • RISC-V
  • Architecture & microprocessors
  • ASICs and SoCs on high-density digital or RF circuit cards
  • Gain hands-on knowledge during design validation and system integration.

Sounds exciting to just get started with expert mentors, doesn’t it? But we are looking for the next generation of learners, inventors, rebels, risk takers, and pioneers.

“Spend your summer working in the future !!”

Outcomes of VSD Online Research IP Design Internship Program

  1. Job opportunities in Semiconductor Industry
  2. Research work can be submitted to VLSI International journals
  3. Participate in Semiconductor International Conference with Internship Research Work
  4. Paper Publications in IEEE Conference and SIG groups
  5. Tape out opportunity and IP Royalty
  6. Interact with world class Semiconductor designer and researchers
  7. Academic professions where more research projects are encouraged.
  8. All the above research and publication work will help colleges and institutes to improve accreditation levels.

Know More Information

VSD – Intelligent Assessment Technology (VSD-IAT)

VSD – Intelligent Assessment Technology (VSD-IAT) is expertly built training platform and is suited for designer requirements. Semiconductor companies understand the value of training automation and Engineer performance enhancement, and do not need to be convinced of the impact of a virtual platform for learning. VSD trainings are quick, relevant, and easy to access from any device at any time zone.

VSD Intern Webinars

VSD Interns made it happen !!

VSD is working towards creating innovative talent pool who are ready to develop design and products for the new tech world. VSD believes in “Learning by doing principle” , and always prepare the student to apply the knowledge learned in the workshops, webinars and courses. We always push our students to work on new designs, test it and work continuously till it becomes the best performing design. Any student who enrolls to VSD community starts working with small design and grows with us and develops a tapeout level design with complete honesty and dedication towards the Work !!

Check out VSD Interns Achievement!

VSDOpen Online Conference

Welcome to the World’s only online conference in Semiconductor Industry VSDOpen Conference. With enormous support and global presence of audience from different segments of industrial lobby and academia made a highly successful event. Evolution is change in the genetic makeup of a population over time, online conference is one kind evaluation everyone adapt soon. 

  • VSDOpen 2022 is an online conference to share open-source research with the community and promote  hardware design mostly done by the student community.
  • VSDOpen 2022 is based on the theme “How to lower the cost to learn, build, and tapeout chips ?”  , which will provide a platform to community to build stronger designs and strengthen the future of Chip design.
  • VSDOpen is envisioned to create a community based revolution in semiconductor hardware technology.
  • The open source attitude is required to bring out the talent and innovation from the community who are in remote part of world and have least access to the technologies.  And now Google support will help to bring the vision to execution by VSD team

VSD Online Course by Kunal Ghosh

VSD offers online course in complete spectrum of vlsi backend flow from RTL design, synthesis and Verification, SoC planning and design, Sign-off analysis, IP Design, CAD/EDA automation and basic UNIX/IT, Introduction to latest technology – RISC-V, Machine intelligence in EDA/CAD, VLSI Interview FAQ’s.

Current Reach – As of 2021, VSD and its partners have released 41 online VLSI courses and was successfully able to teach  ~35900 Unique students around 151 countries in 47 different languages, through its unique info-graphical and technology mediated learning methods.

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