Starting a career in static timing analysis domain, and now actively working on an opensource implementation fllow of RISC-V architecture, has been a journey. For last couple of months, I guess from around March this year, I was hooked to RISC-V buzz which was all over my Linkedin, my messages.
At that point of time, as me and my small team were working on preparing for an open-source conference, I was so focused on finishing what I had on my plate, that I completely ignored the buzz. Result – we had an awesome conference back there in England. Point to be taken – Starve your distractions, feed your focus
Nevertheless, after I finished one, it was time to get hooked to new topic, opensource RISC-V instruction set architecture. When looking at it from a business perspective, it was the coolest shift you could ever see in the VLSI and semi-conductor industry. But this perspective is not what my students were looking for. They (and me too) were looking forward to understanding a bit more about this architecture.
Solution – Be a student as long as you still have something to learn and this will mean all your life
That shift in attitude helped, and I got to interact with the pioneers of RISC-V – Prof. David Patterson. All of you, who have done a bit of research about RISC-V, must have known him. For others, David Patterson is the Pardee Professor of Computer Science, Emeritus at the University of California at Berkeley, which he joined after graduating from UCLA in 1977.
Above all, he’s a great friend who would help you with your doubts, queries and help you fast. This is what makes him rare and easily approachable
That’s when I got a grip of RISC-V, like any other student.
Being an STA and Physical design engineer, it was very important for me to connect RISC-V specification to its implementation on chip. The below image cleared all the smog and my students were able to clearly see RISC-V from bottom STA level, right to the top RISC-V architecture
This was just like how kitchens in McDonalds were built. Customer outside, can see right through the window inside the kitchen and notice how their food is being cooked.
In above image, if you move from right (Hardware) to Left (application program), and then coming from left, if you stop at middle (RISC-V ISA), that’s when you start thinking about this architecture from all angles, like sta, drc, congestion, clock skew, io latency, static and dynamic power, IR and many more.
When we started working on opensource RISC-V implementation flow with our community, our intent was to tap the interface, make sure that first our community understood RISC-V architecture and start thinking to implement it from a hardware or chip layout point of view.
Once we introduced RISC-V architecture in this format to our community, we got so much positive response from industry people, it made us realize that there were many ‘people’ like us who were looking for something like this.
Now with this concept driven implementation, I am eagerly waiting to see it getting fabricated on chip or a product and I believe, you too are…
Here are the links with both online courses in RISC-V:
Part 1b (pre-launched with 5 videos)-