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Monthly Archives: December 2016

A video blog on latch based clock gating and integrated clock gate cell

Hello There’s nothing much to be written about in this blog as this is a video blog. Look at below video which is a sample […]

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Latch based clock gating – clock gating analysis revisited

Hello In my last blog, which received huge response, I talked a simple and efficient technique for clock gating. But it came with an additional […]

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Clock gating analysis – why, what, how?

Hello Now let me first be very clear – This blog is for freshers in static timing analysis domain. This topic had been very confusing […]

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The curious case of ‘interface analysis’!!

Hello This is an important part of static timing analysis, Below is the link: https://www.udemy.com/vlsi-academy-sta-checks-2 I would love to talk about it a lot in […]

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Hey is your laptop ready to design a chip??

Hello Or atleast analyze full chip timing? No…..Then get it ready soon… We will soon be launching course on static timing analysis – part 2 […]

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Art of layout – Euler’s path and stick diagram – Part 3

Hello ….continuing from Part1 and Part2 After the terrible layout we saw in last 2 blogs, without considering euler’s path, its now time to mend […]

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Art of layout – Euler’s path and stick diagram – Part 2

Hello ….lets continue from here So I have been bragging about that ‘art of layout’ is a combination of euler’s path and stick diagram. But […]

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Art of layout – Euler’s path and stick diagram – Part 1

Hello I wrote about euler’s path and stick diagram in two different blogs, but now is the time to show you how are they connected. […]

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16-mask process – Looks complex.. not anymore!! – Part2

Hello ….continued from my previous post….. Once we have the nwell and pwell created, the entire structure is being placed in high temperature furnace and the […]

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16-mask process – Looks complex.. not anymore!! – Part1

Hello If you look into the above image, and wondering how complex it is to build and package a chip, you will change your opinion […]

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