I would love to talk about it a lot in blogs, but unfortunately that will be too much to write, what I have done for you is, I came up with 5 distinct cases where you need to set input and output interface constraints. Yours should be one of them…if not (which I doubt), please intimate me and I might come up with some video on it
Case 1 : c2q and combinational delay for the input side is known, as shown below.
This one’s simple and you just need to add up things and you get the right value of input delays. So you might be wondering about which c2q delay are we talking about, as input delay is from an external driver. Well, look into the above promo image, where I have modeled the input side as virtual flop. Remember, in your constraints, having a set_input_delay w.r.t virtual clock, above images are the one’s where these terms come from.
Case 2 : Input ‘in’ is stable ‘x’ ps before clock rising edge and ‘y’ ps after clock rising edge
This one is tricky, though simple. The blue portion in the timing diagrams are the one’s ‘when your block can change’ and white portion is ‘when outside world can change’ (IO constraints).
Case 3 : setup_time, hold_time and combinational delay for output virtual flop is known
This one, though looks an easy one, needs an in-depth knowledge of reg2reg setup/hold equations.
Case 4 : Output ‘out’ is stable ‘x’ ps before clock rising edge and ‘y’ ps after clock rising edge
Looks familiar to Case 2:?? Not even close for setup…compare the blue and white portion of case 2 and case 4 and you will get it right
Case 5 : Data can change within a window of ‘x’ ps before clock edge and ‘y’ ps after same clock edge (source synchronous interfaces)
You now must be wondering why am I just mentioning all the cases and not writing even a bit of explanation for it…Well, “if you are good at something, never do it for FREE J” – Joker, The Dark Night
Just kidding…if it had been possible, I would had given away all my courses for FREE, but, unfortunately I cannot.