….continued from my previous post…..
Once we have the nwell and pwell created, the entire structure is being placed in high temperature furnace and the ‘well’s are diffused into the substrate, as shown in below 2 images
Next we fabricate the most important terminal of MOS transistor i.e. gate terminal… Remember from one of my ‘Circuit design and SPICE simulation‘ course, I had talked about some important parameters that’s helpful in tuning the threshold voltage. Below image shows the same: Its the ‘doping concentration’ and ‘oxide capacitance’
Let’s see how do we attain that. And here’s mask4 that helps block nwell region and dope p-well with p-type impurity i.e. boron, as shown in below images:
Similarly we dope nwell with n-type impurity i.e Arsenic and use mask 5 for the same as shown in below images:
The oxide present has been through lot of processes like n-type impurity doping, p-type impurity doping, nwell formation, pwell formation and so on, due to which its quality gets reduced. So the original oxide is stripped off using HF acid and then re-grown to give high quality oxide, as shown in below image. This also helps in controlling oxide capacitance, a key parameter to control threshold voltage
While I would like to stop at this point and give you some time to digest what we talked in this blog and the previous one, if interested, you can find all of the above explanations in my newly pre-launched course on custom layout.