VSD 2019 Design Contest (Coming Soon)

Open Source EDA flow Contest

VSD has been continuously developing flows using opensource EDA tools for designs which are close to 25k instance count and tools like qflow/Graywolf/Qrouter/Vesta are quite matured enough to handle these designs. An entire test chip called Raven SoC, which is a RISC-V core, was taped-out using above tool-chain.

With that spirit, we think this is the right time to scale open source EDA tools to handle ~500k instance count design. So, VSD in association with IIT Madras  is introducing “Open-source EDA design contest” Below are 2 class of problems which Industry is facing – Scalability issues and Algorithmic issues.

Teams are invited to Participate and the  deliver best results to win:

• Certification and recognition from IIT Madras RISC-V SHAKTI Team
• 1 LIVE webinar with VSD team on this topic with 50% Lifetime Revenue share

Participants are free to choose any problem of their interest, solve them and best results wins. For details, please click on any below problem statements

1. Scalability Problem Statement
   1. Design Chip Area contest
   2. Pad Placement contest
   3. Pre-place Cells and Power Ring Generation contest
   4. Pre-route Power Nets and Power Grid Generation contest
   5. Default-Rule Based Clock Tree Synthesis contest
   6. Selective Non-Default Rule Based Clock Tree Synthesis Contest
2. Algorithm Problem Statement
   1. Place cells while maintaining blockage
   2. Read parasitics with hierarchy delimiters using openSTA