Place cells while maintaining blockage/PG contest

Problem Statement – Participants are expected to develop a “placement” code which will make sure the logic cells are not placed on pre-placed cells and blockages/PG which were created during Floorplanning, should be retained. Participants are free to use existing opensource placement tool RePlACe

On successful completion, participants with best results will win:

  • Certification and recognition from IIT Madras RISC-V SHAKTI Team
  • 1 LIVE webinar with VSD team on this topic with 50% Lifetime Revenue share

Inputs given for code development and testing:

  • A text file in DEF format with clear definitions of Floorplan i.e. core/die width, pad placement, pre-placed cells, power rings around core/pre-placed cells, placement and routing blockages and other information unplaced/placed/fixed cells
  • Industry grade 180nm PDK’s (standard cells, memories, pads) LEF formats

Expected output from this contest:

A code or bug fix with using existing open-source placement tool RePlACe which will place all logic cells around pre-placed cells, shown in below image

Steps to reproduce this issue:

Step 1) Find a way to parse input DEF file provided by VSD, which has locations, co-ordinates, instance names and many more information of all instances that you see in below image. It can be a command something like below

read_def <input_def_file>

If the DEF file syntax is not in par with standard DEF syntax, issue an error message specifying line number where there is a syntax error

Step 2) Read LEF files provided by VSD

Step 3) Run “RePlAce” tool with above inputs and below is the un-expected output you will observe.

Step 4) Modify or update “RePlAce” source code to get the below expected output

Terms and condition:

  1. You are free to use the source code of existing (and only) opensource tools like RePlAce, magic, qflow, graywolf, qrouter.
  2. Each line of your code needs to be open-sourced and documented