VSD 2019 Read parasitics with hierarchy delimiters using openSTA contest
Problem Statement – Participants are expected to develop a work-around or fix read_parasitics source code of openSTA tool which will be able to read name-mapping/namespace/hierarchical delimiters related industry-grade spef’s
Inputs given for code development and testing:
- A test-case with post-layout RTL netlist, industry grade SPEF, constraints in SDC format and run file to execute openSTA
- Industry grade 180nm PDK’s (standard cells, memories, pads) LIB format
Expected output from this contest:
A code or bug fix with using existing open-source placement tool openSTA which will read any industry grade parasitics
An explanation of the problem statement with an example is below:
After reading parasitics, we get below opensta warning
opensta warning:
Warning: /home/anaghavsd/Desktop/work/to_kunal/mkSoc_wrapper.post_route.spef.max, line 1757581 net U1/lv_result__h66626\[5\] not found.
But when debugged more in SPEF file we see below:
Inside SPEF File:
*2233 U1/lv_result__h66626\[5\]
**Line no. 1757581** 78 *143:55 *2233:13 0.1392269
*D_NET *2233 4.270612
*CONN
*I *2234:Z O *L 0.0 *D dl03d1 *C 664.895 5310.3
*I *2235:A1 I *L 4.929 *C 668.2 5299.12
*N *2233:3 *C 664.28 5312.0
*N *2233:4 *C 664.28 5312.0
*N *2233:5 *C 664.28 5310.84
*N *2233:6 *C 664.28 5310.84
*N *2233:7 *C 666.52 5310.84
*N *2233:8 *C 666.52 5310.84
*N *2233:9 *C 666.52 5300.28
*N *2233:10 *C 666.52 5300.28
*N *2233:11 *C 668.2 5300.28
*N *2233:12 *C 668.2 5300.28
*N *2233:13 *C 668.2 5299.12
*CAP
1 *2234:Z 0.06939172
2 *2235:A1 0.0
3 *2233:3 0.1211474
4 *2233:4 0.06939172
5 *2233:5 0.2014812
6 *2233:6 0.1211474
7 *2233:7 0.2014812
8 *2233:8 0.6075613
9 *2233:9 0.2244984
10 *2233:10 0.6075613
11 *2233:11 0.2244984
12 *2233:12 0.101769
13 *2233:13 0.101769
14 *2233:12 *143:55 0.1392269
15 *2233:13 *143:55 0.1392269
16 *2233:8 *650420:9 0.4570534
17 *2233:10 *650420:9 0.4570534
18 *2233:8 *650438:264 0.0314983
19 *2233:10 *650438:264 0.0314983
20 *2233:10 *650438:263 0.03416146
21 *2233:10 *650438:265 0.09252438
22 *2233:3 *650438:264 0.1183352
*RES
1 *2233:3 *2233:4 6.000001
2 *2233:5 *2233:6 6.000001
3 *2233:7 *2233:8 6.000001
4 *2233:9 *2233:10 6.000001
5 *2233:11 *2233:12 6.000001
6 *2233:13 *2235:A1 6.000001
7 *2233:4 *2234:Z 0.1885714
8 *2233:6 *2233:3 0.4400001
9 *2233:10 *2233:8 3.125714
10 *2233:13 *2233:12 0.4400001
11 *2233:5 *2233:7 0.7485715
12 *2233:9 *2233:11 0.5885715
Opensta timing reports
After loading the verilog, when we use the below commands, we do see the net. So where is the net not found?
% get_nets U1/lv_result__h66626\[5\]
_60ace52700000000_p_Net
% report_checks -digits 4 -fields {capacitance transition_time input_pins nets fanout} -no_line_splits -path_delay max -through [get_nets U1/lv_result__h66626\[5\] ]
Startpoint: U1/dma_dma_ccr_5_reg_16_ (rising edge-triggered flip-flop clocked by CLK)
Endpoint: U1/dma_rg_cpa_5_reg_5_ (rising edge-triggered flip-flop clocked by CLK)
Path Group: CLK
Path Type: max
Fanout Cap Slew Delay Time Description
———————————————————————————————
0.0000 0.0000 clock CLK (rise edge)
6.7393 6.7393 clock network delay (propagated)
0.3830 0.0000 6.7393 ^ U1/dma_dma_ccr_5_reg_16_/CP (sdnrb1)
0.0788 0.5712 7.3104 v U1/dma_dma_ccr_5_reg_16_/Q (sdnrb1)
1 0.0063 U1/MUX_dma_m_xactor_f_rd_addr_enq_1__VAL_6_22 (net)
0.0788 0.0001 7.3106 v U1/U7585/I (buffd3)
0.0839 0.2168 7.5274 v U1/U7585/Z (buffd3)
1 0.0081 U1/n744 (net)
0.0839 0.0002 7.5276 v U1/U78812/I (bufbd4)
0.0707 0.1681 7.6956 v U1/U78812/Z (bufbd4)
1 0.0090 U1/n83296 (net)
0.0707 0.0002 7.6958 v U1/U78466/I (buffd7)
0.0697 0.1758 7.8716 v U1/U78466/Z (buffd7)
2 0.0150 U1/n82946 (net)
0.0697 0.0003 7.8719 v U1/U54722/I (bufbd3)
0.0805 0.1445 8.0164 v U1/U54722/Z (bufbd3)
2 0.0209 U1/n58764 (net)
0.0805 0.0004 8.0169 v U1/U96990/I (buffd1)
0.3433 0.3475 8.3643 v U1/U96990/Z (buffd1)
7 0.0577 U1/n102366 (net)
0.3433 0.0016 8.3660 v U1/DP_OP_3952J2_127_2298/U167/I (buffd1)
0.0853 0.2665 8.6325 v U1/DP_OP_3952J2_127_2298/U167/Z (buffd1)
1 0.0048 U1/DP_OP_3952J2_127_2298/n248 (net)
0.0853 0.0001 8.6326 v U1/DP_OP_3952J2_127_2298/U279/I (dl01d2)
0.1525 0.5225 9.1551 v U1/DP_OP_3952J2_127_2298/U279/Z (dl01d2)
1 0.0057 U1/DP_OP_3952J2_127_2298/n142 (net)
0.1525 0.0001 9.1552 v U1/DP_OP_3952J2_127_2298/U280/I (dl01d2)
0.1497 0.5333 9.6885 v U1/DP_OP_3952J2_127_2298/U280/Z (dl01d2)
1 0.0052 U1/DP_OP_3952J2_127_2298/n143 (net)
0.1497 0.0001 9.6886 v U1/DP_OP_3952J2_127_2298/U755/A2 (nr02d0)
0.8731 0.4852 10.1737 ^ U1/DP_OP_3952J2_127_2298/U755/ZN (nr02d0)
1 0.0149 U1/DP_OP_3952J2_127_2298/n671 (net)
0.8731 0.0004 10.1742 ^ U1/DP_OP_3952J2_127_2298/U119/I (dl01d1)
0.2248 0.7421 10.9163 ^ U1/DP_OP_3952J2_127_2298/U119/Z (dl01d1)
2 0.0121 U1/DP_OP_3952J2_127_2298/n138 (net)
0.2248 0.0004 10.9167 ^ U1/DP_OP_3952J2_127_2298/U649/A2 (an12d1)
0.3693 0.2971 11.2137 ^ U1/DP_OP_3952J2_127_2298/U649/Z (an12d1)
2 0.0300 U1/DP_OP_3952J2_127_2298/n669 (net)
0.3694 0.0013 11.2150 ^ U1/DP_OP_3952J2_127_2298/U643/A2 (nd02d0)
0.3339 0.2181 11.4331 v U1/DP_OP_3952J2_127_2298/U643/ZN (nd02d0)
3 0.0128 U1/DP_OP_3952J2_127_2298/n673 (net)
0.3339 0.0002 11.4333 v U1/DP_OP_3952J2_127_2298/U555/I (inv0d1)
0.1413 0.1331 11.5664 ^ U1/DP_OP_3952J2_127_2298/U555/ZN (inv0d1)
1 0.0054 U1/DP_OP_3952J2_127_2298/n678 (net)
0.1413 0.0001 11.5665 ^ U1/DP_OP_3952J2_127_2298/U658/B2 (aoi21d1)
0.1942 0.1247 11.6912 v U1/DP_OP_3952J2_127_2298/U658/ZN (aoi21d1)
2 0.0133 U1/DP_OP_3952J2_127_2298/n686 (net)
0.1942 0.0003 11.6915 v U1/DP_OP_3952J2_127_2298/U667/B1 (oai21d1)
0.8122 0.4559 12.1474 ^ U1/DP_OP_3952J2_127_2298/U667/ZN (oai21d1)
2 0.0200 U1/DP_OP_3952J2_127_2298/n710 (net)
0.8122 0.0009 12.1483 ^ U1/DP_OP_3952J2_127_2298/U684/B1 (aoi21d2)
0.1328 0.3757 12.5240 v U1/DP_OP_3952J2_127_2298/U684/ZN (aoi21d2)
2 0.0327 U1/DP_OP_3952J2_127_2298/n758 (net)
0.1328 0.0013 12.5253 v U1/DP_OP_3952J2_127_2298/U685/I (inv0d2)
0.1592 0.1115 12.6369 ^ U1/DP_OP_3952J2_127_2298/U685/ZN (inv0d2)
3 0.0225 U1/DP_OP_3952J2_127_2298/n730 (net)
0.1592 0.0005 12.6374 ^ U1/DP_OP_3952J2_127_2298/U690/A1 (xn02d1)
0.1289 0.2710 12.9085 v U1/DP_OP_3952J2_127_2298/U690/ZN (xn02d1)
1 0.0084 U1/DP_OP_3952J2_127_2298/n32 (net)
0.1289 0.0002 12.9086 v U1/DP_OP_3952J2_127_2298/U23/I (buffd1)
0.0917 0.2155 13.1242 v U1/DP_OP_3952J2_127_2298/U23/Z (buffd1)
1 0.0060 U1/DP_OP_3952J2_127_2298/n231 (net)
0.0917 0.0001 13.1243 v U1/DP_OP_3952J2_127_2298/U124/I (dl03d1)
0.3833 2.3981 15.5224 v U1/DP_OP_3952J2_127_2298/U124/Z (dl03d1)
1 0.0030 **U1/lv_result__h66626[5]** (net)
0.3833 0.0000 15.5224 v U1/U26534/A1 (aor22d1)
0.1082 0.2456 15.7680 v U1/U26534/Z (aor22d1)
1 0.0073 U1/n5537 (net)
0.1082 0.0002 15.7681 v U1/dma_rg_cpa_5_reg_5__U3/I0 (mx02d4)
0.1199 0.3415 16.1096 v U1/dma_rg_cpa_5_reg_5__U3/Z (mx02d4)
1 0.0074 U1/n23827 (net)
0.1199 0.0001 16.1098 v U1/U78973/I (dl03d1)
0.4280 2.4393 18.5490 v U1/U78973/Z (dl03d1)
1 0.0049 U1/n83458 (net)
0.4280 0.0000 18.5490 v U1/U119807/I (bufbd4)
0.0775 0.2558 18.8048 v U1/U119807/Z (bufbd4)
1 0.0118 U1/n119222 (net)
0.0775 0.0002 18.8050 v U1/U119809/I (buffd2)
0.0611 0.1311 18.9362 v U1/U119809/Z (buffd2)
1 0.0053 U1/n119224 (net)
0.0611 0.0001 18.9363 v U1/U119808/I (buffd3)
0.0733 0.2024 19.1387 v U1/U119808/Z (buffd3)
1 0.0033 U1/n119223 (net)
0.0733 0.0001 19.1388 v U1/dma_rg_cpa_5_reg_5_/D (sdnrb1)
19.1388 data arrival time
20.0000 20.0000 clock CLK (rise edge)
6.7002 26.7002 clock network delay (propagated)
-0.9000 25.8002 clock uncertainty
0.0000 25.8002 clock reconvergence pessimism
25.8002 ^ U1/dma_rg_cpa_5_reg_5_/CP (sdnrb1)
-0.4036 25.3966 library setup time
25.3966 data required time
———————————————————————————————
25.3966 data required time
-19.1388 data arrival time
———————————————————————————————
6.2578 slack (MET)
Steps to run testcase
- Download
- tar -xvzf testcase.tar.gz
- cd testcase
- sta -f mkSoc_wrapper.post_route.osu.cmd
Testcase:
https://1drv.ms/u/s!Ai4WW_jutenggas652Vq2moOnyRA-g
You can check some of below nets
% get_nets U1/qspi1$slave_rdata[63]
_e0bebf0700000000_p_Net
% get_nets U1/qspi1/v__h15039[17]
_f06ed30700000000_p_Net
Terms and condition:
- You are free to use the source code of existing (and only) opensource tools like openSTA, openTimer.
- Each line of your code needs to be open-sourced and documented
