read_sdc – clock constraints
read_sdc is been considered as a very critical command in EDA world, as this is the command which defines your specifications, and if not written and interpreted correctly, can lead a huge delay in tapeout cycle.
Tag Archives: design rules
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Art of layout – Euler’s path and stick diagram – Part 3
Hello ….continuing from Part1 and Part2 After the terrible layout we saw in last 2 blogs, without considering euler’s path, its now time to mend […]
Art of layout – Euler’s path and stick diagram – Part 2
Hello ….lets continue from here So I have been bragging about that ‘art of layout’ is a combination of euler’s path and stick diagram. But […]
Art of layout – Euler’s path and stick diagram – Part 1
Hello I wrote about euler’s path and stick diagram in two different blogs, but now is the time to show you how are they connected. […]
design rule check – looks complex, but easy to code..!!
…and that’s exactly the perception that I am determined to solve. People in my physical design course have had a glimpse of design rule check […]
Maze Routing – Lee’s Algorithm
Lee’s Algorithm guarantees there is exists a valid path and it’s the shortest path.
But, this algorithm is too time and memory consuming, To overcome, these short-comings, there are other more advanced algorithms like Line search Algorithm, Steiner Algorithms, etc.
