MAGIC Layout FAQ – psubstratecontact and nsubstratecontact
Hey There, Now that it’s clear, that we can tapeout using open-source EDA tools (referring to recent RavenSoC tapeout by Efabless Corp. Pvt. Ltd. using […]
Tag Archives: 180nm technology node
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eFabless is back…with synth/PD/DRC/LVS…and a working CHIP
A working chip is all using opensource EDA tools (no more license fee). Of course, its taped-out in 180nm technology. But who knows, this might be just the beginning. Upcoming blogs will talk more about the commercial angle of this. Let’s see how it is going to benefit student/professionals/innovators community
I am hidden, but I exist-Dynamic power dissipation in CMOS
Meet me, I am “hidden power” Dynamic power dissipation in CMOS When we are asked about dynamic power dissipation, below 2 things just appear at […]
Hey, its time you take charge of your design!!
….And this is something which I can show you using the newly launched open-source EDA tool “eSim (FOSSEE IITB Project)”. Let’s assume for a moment, […]
Did you scale down? – high interconnect impedance – CCS timing!!
You see how every sentence in the title is connected!!! As you are aware about the big launch on “CCS Library” course, I just wanted […]
