 # Generated clock & master clock.. Let’s make it simple – Part 2

hello

Based on the responses of previous post of Generated clock & master clock … Let’s make it simple!! – Part 1, I am very excited to write part 2 of this, where I will try to define generated clocks for a divide-by-3 and ‘inverted’ divide-by-2 circuit.
Let’s take a simple divide-by-3 circuit and below is how its waveform at output will look like (assuming a non-50% duty cycle). The output clock period is 3 times the input clock period and hence, frequency is divided-by-3. (It would be a great idea to show the interiors of divide-by-3 circuit. Stay with me and I will do that in following posts) So, now, if we need to write this gen_clock definition, its simple. Just fill out the table and below is what we get This shows a perfect usage of ‘edge’ option. For circuits producing a clock waveform which has non-50% duty cycle, the edge option can be very well used to define an output clock and can also be propagated throughout the circuit. It just says, that 1st rise edge of gen_clock arrives at 1st edge of master_clock, 1st fall edge of get_clock arrives at 5th edge of master_clock and 2nd rise edge (which completes 1 clock cycle) arrives at 7th edge of master_clock
Pay attention to the words above. I am using ‘rise’ and ‘fall’ words for defining gen_clock (as these words are the one’s that completes one clock cycle) and I am using just the word ‘edge’ for master_clock and ‘edge’ can be either rise or fall, doesn’t matter from gen_clock definition perspective
Now, to explore other options of this table, let’s look into another circuit specification, where output is inverted and divide-by-2 of input waveform.   