Myself, Reset Synchronizer – I synchronize the asynchronous

Hi Everyone,

My name is ‘Reset Synchronizer’. I have been tasked to do a very specific job. Though, I look to be a very small piece of circuit, I help the whole design to get rested without any violations. You can think of my job to be very similar and as critical as my brother ‘The clock’. Even I my own tree and my own network, just like my brother has. The only difference is, I am not as strict on skew, as my brother is. I am a bit flexible, which makes me even prouder and lovable by designers 🙂

Let me try to show you in below image, what happens when you try to reset design without me, asynchronously

My close friend (also the one who can’t stay without me, stay with me till end of this post) ‘rst_n’ looks to be very confident while asserting himself onto whole design and very successfully resets the complete design. But he creates lots of problems for the whole design, while de-asserting himself. How? Whenever he tries to de-assert himself near active edge of clock, he creates violations, doesn’t satisfy setup/hold requirements of flops, corrupts their data and creates meta-stability

That’s when, these flops, came to me asking for a solution. I gave it a lot of thought, and tried to convince my friend ‘rst_n’ to allow me come and stand firmly in between him and the design. He’s my friend, and so I should be saving him, right. I mean, that’s friends are for….

So I came in between, like shown in below image….

Now, I have a very superior connection, with Vdd directly connecting me at my ‘D’ input and my friend ‘rst_n’ connecting with me at my ‘RST’ pin.

Now, I ask my friend ‘rst_n’ to first reset me, so that I go to a ‘0’ state, and then first de-assert me, so that only I corrupt my data (which is ok for me). My connections are so strong (see the second flop rs2), that I can easily overcome my meta-stability in 2 clock cycles as shown below:

Not only that, I also take forward this ‘mst_rst_n’ signal to all flops in the design, like a tree, just like the clock, as shown in below image. Now that I look just like any reg2reg path, my other friends, flip-flops, should just check me like any other reg2reg setup and hold violation

Since that now I am being treated with same dignity and respect that my brother ‘The clock’ is being treated, the violations produced due to my signal ‘mst_rst_n’ is being given a special name. I am not called setup or hold violation, I am being called as the proud ‘reset recovery’ and reset removal’ violations.

From the above whole scenario, I have learnt one major thing in my life which is being very well composed as below quote by ‘Katrina Mayer’:

Even a small act of kindness can make a big difference in someone’s world

Do one small act of kindness today …. Register in my courses 🙂

Registration for Ethical RISC-V IoT Workshop

Welcome to Ethical RISC-V IoT Workshop

The “Ethical RISC-V IoT Workshop” at IIIT Bangalore, organized in collaboration with VSD, is a structured, educational competition aimed at exploring real-world challenges in IoT and embedded systems. Participants progress through three stages: building an application, injecting and managing faults, and enhancing application security. The event spans from May 9 to June 15, 2024, culminating in a showcase of top innovations and an award ceremony. This hands-on hackathon emphasizes learning, testing, and securing applications in a collaborative and competitive environment.

Rules :
  1. Only for Indian Student whose college is registered under VTU
  2. Only team of 2 members can Register
  3. Use only VSDSquadron Mini resources for product development
Awards :
  1. Prize money for final 10 Team
  2. 3 Winner team’s Product will be evaluated for Incubation
  3. 7 consolation prizes
  4. Completion Certificate to final round qualifier
  5. Chance to build a Proud Secured RISC-V Platform for India

Date for Registration : 9th May - 22nd May, 2024
Hackathon Inauguration : 23rd May 2024

VSDSquadron (Educational Board)

VSDSquadron, a cutting-edge development board based on the RISC-V architecture that is fully open-source. This board presents an exceptional opportunity for individuals to learn about RISC-V and VLSI chip design utilizing only open-source tools, starting from the RTL and extending all the way to the GDSII. The possibilities for learning and advancement with this technology are limitless.

Furthermore, the RISC-V chips on these boards should be open for VLSI chip design learning, allowing you to explore PNR, standard cells, and layout design. And guess what? vsdsquadron is the perfect solution for all your needs! With its comprehensive documentation and scalable labs, thousands of students can learn and grow together.

VSD HDP (Hardware Design Program) Duration-10 Week

With VSD Hardware Design Program (VSD-HDP),  you have the opportunity to push the boundaries of what exist in open source and establish the new benchmark for tomorrow.

It will leverage your degree in Electrical or Computer Engineering to work with

  • Programmable logic
  • Analog/ digital IP
  • RISC-V
  • Architecture & microprocessors
  • ASICs and SoCs on high-density digital or RF circuit cards
  • Gain hands-on knowledge during design validation and system integration.

Sounds exciting to just get started with expert mentors, doesn’t it? But we are looking for the next generation of learners, inventors, rebels, risk takers, and pioneers.

“Spend your summer working in the future !!”

Outcomes of VSD Online Research IP Design Internship Program

  1. Job opportunities in Semiconductor Industry
  2. Research work can be submitted to VLSI International journals
  3. Participate in Semiconductor International Conference with Internship Research Work
  4. Paper Publications in IEEE Conference and SIG groups
  5. Tape out opportunity and IP Royalty
  6. Interact with world class Semiconductor designer and researchers
  7. Academic professions where more research projects are encouraged.
  8. All the above research and publication work will help colleges and institutes to improve accreditation levels.

Know More Information

VSD – Intelligent Assessment Technology (VSD-IAT)

VSD – Intelligent Assessment Technology (VSD-IAT) is expertly built training platform and is suited for designer requirements. Semiconductor companies understand the value of training automation and Engineer performance enhancement, and do not need to be convinced of the impact of a virtual platform for learning. VSD trainings are quick, relevant, and easy to access from any device at any time zone.

VSD Intern Webinars

VSD Interns made it happen !!

VSD is working towards creating innovative talent pool who are ready to develop design and products for the new tech world. VSD believes in “Learning by doing principle” , and always prepare the student to apply the knowledge learned in the workshops, webinars and courses. We always push our students to work on new designs, test it and work continuously till it becomes the best performing design. Any student who enrolls to VSD community starts working with small design and grows with us and develops a tapeout level design with complete honesty and dedication towards the Work !!

Check out VSD Interns Achievement!

VSDOpen Online Conference

Welcome to the World’s only online conference in Semiconductor Industry VSDOpen Conference. With enormous support and global presence of audience from different segments of industrial lobby and academia made a highly successful event. Evolution is change in the genetic makeup of a population over time, online conference is one kind evaluation everyone adapt soon. 

  • VSDOpen 2022 is an online conference to share open-source research with the community and promote  hardware design mostly done by the student community.
  • VSDOpen 2022 is based on the theme “How to lower the cost to learn, build, and tapeout chips ?”  , which will provide a platform to community to build stronger designs and strengthen the future of Chip design.
  • VSDOpen is envisioned to create a community based revolution in semiconductor hardware technology.
  • The open source attitude is required to bring out the talent and innovation from the community who are in remote part of world and have least access to the technologies.  And now Google support will help to bring the vision to execution by VSD team

VSD Online Course by Kunal Ghosh

VSD offers online course in complete spectrum of vlsi backend flow from RTL design, synthesis and Verification, SoC planning and design, Sign-off analysis, IP Design, CAD/EDA automation and basic UNIX/IT, Introduction to latest technology – RISC-V, Machine intelligence in EDA/CAD, VLSI Interview FAQ’s.

Current Reach – As of 2021, VSD and its partners have released 41 online VLSI courses and was successfully able to teach  ~35900 Unique students around 151 countries in 47 different languages, through its unique info-graphical and technology mediated learning methods.

Enquiry Form