Hi “Pictures speak it all” Finally, we all did it – VSDOpen – first ever online VLSI conference. Very close to a real one – […]
A proud moment for our company VLSI System Design Corporation Pvt. Ltd., for my colleague Anagha Ghosh and for myself (See image below)
Our company’s first paper on IEEE explore for technology mediated learning – World’s prestigious institute for engineering and technology innovation. Here’s the link for the paper
SPI model is a master/slave model. There’s some SPI master which determines who gets to transmit and who gets to receive. The output from SPI master is called MOSI (Master Out Slave In). If you have 2 slaves, slave 1 and slave 2, as shown below, MOSI goes to all the slaves .Then you have another line MISO (Master In Slave Out). All the wires are connected, as shown in below image. Then you have a master only function called SCLK, which goes to all the slaves. Now also, there must be a slave select (SS) for S1 and a slave select for S2.