Can you approve my floorplan?
Just to give you some background, picoSoC is an example SoC using PicoRV32, and PicoRV32 is a size-optimized RISC-V CPU which implements RV32IMC instruction set architecture.
Tag Archives: performance
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The beauty of slack-based timing ECO
A timing ECO should be power, performance and area aware and that was the crux of this webinar, where we discussed several strategies about how to do effective ECO as an expert .Slack based ECO is a beautiful strategy which helps you to achieve your timing target, while helping you to reduce on power and area
PPA (power, performance, area) card
A PPA card like the above, is something which every VLSI engineer should be carrying like a business card. Why? Right from RTL to synthesis to PNR to signoff, we do things like upsize, downsize, VT swap, and many more, and all these factors impacts or tweaks your design PPA in one way or the other.
Let’s take an example of ‘downsize’
Report QOR (Quality Of Results)
Above images plays a huge role in closing on gaps between a tool user (customers who use the tool) and product engineer/manager (one who manages the tool TCL interface)
Regular buffer v/s Clock buffer – Part 3
Hello After my last post on “Regular buffer v/s Clock buffer – Part 2“, I received several mails on having a video of the post. […]
Regular buffer v/s Clock buffer – Part 2
Hello I feel lucky and blessed, after my last post on “Regular buffer v/s Clock buffer – Part 1“, as I received couple of emails, […]
