Timing-driven optimization is imperative for the success of closure flows. The optimization engine applies changes to the design and estimates circuit delays quickly and accurately to improve timing, area, and power performance. This procedure is inherently complex and computationally challenging.
VSDOpen 2018 Keynote 1 : A New Golden Age for Computer Architecture: History, Challenges, and Opportunities
A New Golden Age for Computer Architecture: History, Challenges, and Opportunities, David Patterson, UC Berkeley and Google, October 26, 2018Full Turing Lecture: https://www.acm.org/hennessy-patterson-turing-lecture
The above waterfall diagram is representing a sequence of instructions that are fetched from memory and how they progress to the various stages of pipeline. In the above diagram you got program counter (P), fetch (F), decode (D), register read (R), execute (E) and register write (W). We fetch one instruction at a time. Potentially, you can fetch multiple instructions at a time, which would be a super-scalar architecture.
ABI (application binary interface), as the name says, is an interface, that helps programs access system hardware and services.RISC-V architecture has 32 registers (we explained, in detail, why this architecture has 32 registers in our online course). Application programmer, can access each of these 32 registers through its ABI name, for example, you need know the value of stack pointer or move the stack pointer, all you need to do is “addi sp, sp, -16”, where ‘sp’ is the ABI name of stack pointer.