Hey There – Think about it!!! Today’s version of open-source EDA tools, work very well for hierarchical designs sub-25k instance count. For hierarchical designs ~500k instance count, what if, we develop code which will enable users to design/decide chip area based on width and height of chip OR utilization factor […]Continue reading
Design Verification is critical to proving functional correct- ness and establishing confidence in a design. Several stud- ies from industry and academia, particularly over the course of the last two decades, have explored various verifica- tion methodologies that fall somewhere between dynamic or purely static formal approaches.
System-on-Chips (SoCs) today have become extremely complex structures housing heavily optimized cores, count- less peripherals, and large interconnect fabrics. Even re- stricting ourselves to just verifying the microprocessor, the state space to be verified is enormous and cannot be exhaus- tively explored in any finite amount of time. Manually writ- ten tests, while effective at capturing some complexities of design intent, suffer from the fact that they are expensive in cost and time required to develop them. Random stimulus methods perform better because they eventually cover many cases. Most new ideas in dynamic verification over the last two decades have largely been towards semi formal verifi- cation methodologies such as coverage driven verification and constrained test generation. In this paper, we explore an approach to dynamic functional verification that we use at the RISE lab, IIT Madras for the verification of the RISC-V based Shakti cores.
Hello You guessed it right. I am referring to ‘fabless’ model of semiconductor business… Here I am referring to one of my post, which had an open ended question “My biggest challenge – Do I have money to build better chips” ‘Fabless’ model sounds very simple and easy concept, well, […]Continue reading