History etched with VSDOpen2018 – First VLSI online conference….
Hi “Pictures speak it all” Finally, we all did it – VSDOpen – first ever online VLSI conference. Very close to a real one – […]
Tag Archives: clock gating
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Paper 6: Formally Verifying WARP-V, an Open-Source TL-Verilog RISC-V Core Generator
This paper introduces TL-V erilog and W ARP-V and then describes the formal verification of WARP-V using riscv-formal, a formal verification framework for RISC-V. Timing-abstraction and transaction-level design are showing significant benefits for hardware modeling, but this is the first demonstration of their benefits for verification modeling. As evidence of these benefits, the verification of all RISC-V configurations of WARP-V is accomplished in a single page of code.
Latch based clock gating – clock gating analysis revisited
Hello In my last blog, which received huge response, I talked a simple and efficient technique for clock gating. But it came with an additional […]
