# Latch timing – Beg, borrow or steal !!

Sounds crude … This is how it functions. Well, in my opinion, it’s not as crude as it sounds, but a very smart way to achieve high performance in some critical cases. Let’s start with what it looks like. A latch is nothing but a part of a flipflop. In some of my past posts, I have mentioned the construction of a flipflop using negative and positive latch. So now, just take the positive latch out of it, and below is how a positive latch and its connections looks like (FYI: there are even better configurations of latches available. The below is just an example)

During the positive ‘level’ of clock signal, the transmission gate Tr4 is OPEN, and Qm flows till Q, i.e. whatever is the input, is the output. Let’s take a pause over here:

This behavior of latch is something we are looking for few critical paths of a high-performance design. This is what allows us to ‘steal’ some portion of the clock to meet timing for critical paths. Question is how it looks like? If now you consider one of my circuits, that I have been using in my STA-2 course, I have replaced the capture flop with a latch L2, and timing diagram looks something like below:

The launch is a edge triggered flip flop, where the capture flop is a latch, whose active level is shown from edge4 to edge5. Now the above path has a violation with slack as -38.36ps. And let’s say, this is the path which has been optimized to the highest level. What do we do now? In the above case, since capture is a latch, and it remains active for the entire high level of clock, we can ‘borrow’ some time from the clock cycle, and meet this path timing with exact ‘zero’ slack as shown below

Isn’t that good news? Well, not good enough…. why?

When you borrow something, you need to return something. In this case, the next stage (if there had been one), will receive 38.36ps less, instead of full clock cycle i.e. (T – 38.36) ps. Which means, the next stage must be really short and fast, because now is has less of clock period available. And the slack equation for the stage following L2 flop will look something like below:

Nothing comes for free. Not even borrowing some few ps from clock. This brings me to an interesting quote written by ‘Benjamin Franklin

If you would the value of money, go try to borrow some; for he that goes a-borrowing goes a-sorrowing

Replace ‘money’ by ‘time’ over here, and you would get the above concept….

Till then, enjoy the courses and blogs, and happy learning !!

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## One Comment

1. Ankit

Hi, your explanation is correct. Data launched at N posedge of ff1 should be checked for setup after 1.5T, at a negedge of latch, though the tool by default considers the immediate negedge of latch (after 0.5T) for setup check. And even practically, data launched at N+1 posedge of flop will disturb the previous Nth data at the negedge of latch. How to deal with this?