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On-Chip Variation (OCV) – Part 2

Hello Today, I was a guest speaker at one of the biggest Technical Conference held in Bangalore, and luckily I met few people who had […]

On-Chip Variation (OCV) – Part 1

Hello Ever thought what’s an interviewer’s favorite questions to rip you off – all of my previous post :). And On-Chip Variation (OCV) is one […]

Regular buffer v/s Clock buffer – Part 3

Hello After my last post on “Regular buffer v/s Clock buffer – Part 2“, I received several mails on having a video of the post. […]

Regular buffer v/s Clock buffer – Part 2

Hello I feel lucky and blessed, after my last post on “Regular buffer v/s Clock buffer – Part 1“, as I received couple of emails, […]

Regular buffer v/s Clock buffer – Part 1

Hello, Everyone, who’s been a part of physical design or STA, must have definitely gone through this. When I thought about it, like 5 years […]

Clk-to-q delay, library setup and hold time – Part 2

Hello, This is in continuation to the previous post, where I explained about transistor level implementation of negative and positive latch. In this post, I […]

Clk-to-q delay, library setup and hold time – Part 1

Hello, I have been receiving multiple queries on what is clk-to-q delay, how’s it different from library setup time and library hold time, etc. I […]

SPEF Format – Part 3

Hello, I realized last night, that I was celebrating my work anniversary. Thanks Linkedin for reminding me that :). And, thought, let’s celebrate this one […]