Euler’s path, euler’s circuit, pull-up, pull-down, vlsi layout – Are all connected? – Part1
Yes….they are….Find out more about it in my custom Layout course: While you still decide to take my layout course or not, I would like […]
Monthly Archives: February 2017
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Hey, its time you take charge of your design!!
….And this is something which I can show you using the newly launched open-source EDA tool “eSim (FOSSEE IITB Project)”. Let’s assume for a moment, […]
eSim Tool – From 2015 Vision to 2017 Reality
If you had been following me on linkedin or Udemy, you would have had received an announcement from me in the year 2015, where I […]
Let’s talk about currents – Punch through effect..
And it’s important, as this will set a back-ground for my upcoming new course on “CCS Timing Libraries”. So, in my last blog, we talked […]
Did you scale down? – high interconnect impedance – CCS timing!!
You see how every sentence in the title is connected!!! As you are aware about the big launch on “CCS Library” course, I just wanted […]
vlsisystemdesign.com – re-created, revamped and re-published – its cooler now!!
vlsisystemdesign.com – The website which started with basic hand-drawn diagrams and blogs is now being re-created, revamped and re-published. This time, it more cooler and […]
Timing libraries – This is where body and soul meets…!!
Get geared up for my next “to be” launched course on CCS timing libraries – Constructs and characterization. Let me be a bit frank here […]
“20ps < clock_tran < 60ps”, ever wondered what’s the real reason?
I am sure you must have…. This blog will just walk you through the reasons using cool images from my latest course on “Static Timing […]
Latch timing – Beg, borrow or steal !!
Sounds crude … This is how it functions. Well, in my opinion, it’s not as crude as it sounds, but a very smart way to […]
Myself, Reset Synchronizer – I synchronize the asynchronous
Hi Everyone, My name is ‘Reset Synchronizer’. I have been tasked to do a very specific job. Though, I look to be a very small […]
