
Skywater130 Spec to GDS workshop details
You might have seen the above image in one form or another, in different our blogs or VSD websites. Every trapezoid in above image is […]
You might have seen the above image in one form or another, in different our blogs or VSD websites. Every trapezoid in above image is […]
Hi “Pictures speak it all” Finally, we all did it – VSDOpen – first ever online VLSI conference. Very close to a real one – […]
This paper describe a rapid backend process flow (synthesis, placement, STA, routing) and top level integration to implement a small RTL IP into a tapeout ready chip using the Efabless online platform [1]. The full process is completed in less than 3 hours. The IP implemented is a configurable frequency divider
online VLSI courses using open-source tools, VSDSYNTH, our new product (currently in beta testing) is unique UI that will take in inputs in form of RTL netlist and read standard SDC format constraints. The UI will generate synthesized netlist and pre-layout timing reports, hereby giving you first hand information on the quality of your RTL design