Power rail discontinuity – We would like to have continuous power rail.N- and P-diffusion discontinuity – We would like to have continuous diffusion. For my Physical design friends, remember, we add “FILLER” cells at the end of routing, and you always wondered why we are doing so.Small substrate contacts – Except for inverter, all substrate contacts are single width, which will create high resistance path for current, thus increasing “Clk-to-Q” delay.Hanging metal1 – If you see for the NAND gate outputs, there is lot of hanging metal1.
Symposium V – Machine Intelligence in EDA/CAD applications- Let’s investigate a simple Wire Resistance Estimate (WiRE) model
This is common design automation problem which is used for estimating timing and power characteristics for analysis and implementation for many steps in ASIC flow. We will restrict our scope to physical implementation only, where known quantity is “length” of wire and resistance is predicted.
Hello, I realized last night, that I was celebrating my work anniversary. Thanks Linkedin for reminding me that :). And, thought, let’s celebrate this one […]
Hello, Hope you liked my previous post on “SPEF Format”, and, there had been 4 days since my last post, so I believe the previous […]
Hello, So, this has been due for long time. May be because of tight tape out deadlines, this very important piece of Physical Design flow […]