placement – VLSI System Design

Ever heard of Chip Design Pentagon?

Know what Pentagon is? It is a plane figure which has 5-straight sides and 5-angles. For a perfect pentagon, it needs all its sides and angles to be the same, till the last decimal. Do you know what is the similarity between pentagon and our upcoming workshop “Advanced Physical Design workshop using OpenLANE/SKY130”? Look above image and you would guess it right. It is a perfect blend of topics where even a fresher can jump-start his/her career in chip design in just 5-days

Re-define pad placement using open-source EDA

Hey There – Think about it!!! Last week, we shared our idea and vision of “How to define the width and height of core and […]

History etched with VSDOpen2018 – First VLSI online conference….

Hi “Pictures speak it all” Finally, we all did it – VSDOpen – first ever online VLSI conference. Very close to a real one – […]

Rapid Physical IC Implementation

“Rapid Physical IC Implementation and Integration using Efabless Platform”. This paper describe a rapid backend process flow (synthesis, placement, STA, routing) and top level integration to implement a small RTL IP into a tapeout ready chip using the Efabless online platform

Symposium IV – Place and route of digital IC’s for best PPA

A good takeaway from above is which is the best flow – Well, there is no single answer to this. You can use “flow 1”, if your organization is constrained by cost and comparable performance, and you can go for “flow 2” if performance is the criteria.

eFabless is back…with synth/PD/DRC/LVS…and a working CHIP

A working chip is all using opensource EDA tools (no more license fee). Of course, its taped-out in 180nm technology. But who knows, this might be just the beginning. Upcoming blogs will talk more about the commercial angle of this. Let’s see how it is going to benefit student/professionals/innovators community

Tag Archives: placement

Re-define pad placement using open-source EDA

Rapid Physical IC Implementation

Let’s predict future…And built it…

Timing libraries – This is where body and soul meets…!!

VSDSquadron (Educational Board)

VSD HDP (Hardware Design Program) Duration-10 Week

VSD – Intelligent Assessment Technology (VSD-IAT)

VSD Intern Webinars

VSD Interns made it happen !!

VSDOpen Online Conference

VSD Online Course by Kunal Ghosh

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