You might have seen the above image in one form or another, in different our blogs or VSD websites. Every trapezoid in above image is […]
The above waterfall diagram is representing a sequence of instructions that are fetched from memory and how they progress to the various stages of pipeline. In the above diagram you got program counter (P), fetch (F), decode (D), register read (R), execute (E) and register write (W). We fetch one instruction at a time. Potentially, you can fetch multiple instructions at a time, which would be a super-scalar architecture.
Hello Long time … since my last post …. Reason : Hopefully, I have given enough time for you to get hold on my previous […]
Hello If you have read through my previous posts on the above topic, things have seriously become interesting over here. I mean, isn’t that exciting, […]
Hello I will derive the CMOS VTC in few steps, and below is the first one. We did derive the below equations sometime back, and […]