The horrible std cell ever designed by me….

Power rail discontinuity – We would like to have continuous power rail.N- and P-diffusion discontinuity – We would like to have continuous diffusion. For my Physical design friends, remember, we add “FILLER” cells at the end of routing, and you always wondered why we are doing so.Small substrate contacts – Except for inverter, all substrate contacts are single width, which will create high resistance path for current, thus increasing “Clk-to-Q” delay.Hanging metal1 – If you see for the NAND gate outputs, there is lot of hanging metal1.

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Clk-to-q delay, library setup and hold time – Part 2

Hello, This is in continuation to the previous post, where I explained about transistor level implementation of negative and positive latch. In this post, I will showing images on transistor level implementation of flip-flop and finally, we will nail down the 3 terms i.e. clk-to-q delay, library setup and library […]

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Clk-to-q delay, library setup and hold time – Part 1

Hello, I have been receiving multiple queries on what is clk-to-q delay, how’s it different from library setup time and library hold time, etc. I mentioned in my discussions, that the videos on CMOS digital circuit will be uploaded soon, but looks like, it might take some time, and hence […]

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