RISC-V Workshop @IIT Madras – Day 2

And suddenly you know: It’s time to start something new and trust the magic of beginnings” Meister Eckhart….he was so right…

Hey There,

Though 2-day RISC-V workshop has come to an end at IIT Madras, trust the magic of beginnings. Not only, this workshop was a boost to RISC-V ecosystem, it was also a boost to Indian start-up ecosystem, where now, me and you, together can start a processor company, without much of legal hassles.

Why so?

ISA is opensource, many RISC-V cpu cores are available at gitbub and free to download, and on top of that, if I say, we are on the path, where you can now implement your core using opensource EDA tools…Wowww….That’s a new exciting never-seen-before model in semi-conductor industry. All you need is a push from within and think like an “entrepreneur” – By the way, that’s how Amazon, Facebook, Google and even Apple had started-up….

Key highlights of Day 2 were Ashish Patra’s talk. He is Principal R&D engineer from Western Digital, and his talk focused to 2 important things – first was regarding current capabilities of Linux on RISC-V, which would serve a guide for developers to make design choices for prototyping and performance bench-marking. And second – it serves as a guide for new developers who are willing to start contributing towards RISC-V kernel port

Next, Muhammad Arsath from IIT Madras presented his evaluation work on data-leaks on SHAKTI C-Class, which is a RISC-V based microprocessor. Vinod and Gopinath from IIT Madras described more about “Risecreek” (test SoC around SHAKTI-C64). “Risecreek” has been taped out using Intel 22nm technology node. Luke wrapped up pre-lunch talk on SHAKTI M-Class Libre RISC-V SoC, that outlined plan on how to design and bring to market a mass-volume commercial System-on-Chip. These talks did show the energy and excitement behind India’s RISC-V SoC ecosystem.

To add to above, Paul George from IIT Madras presented Shakti Lockstep Verification Framework (SLSV) for dynamic verification and post-silicon validation. The good part – SLSV is completely open-source framework being developed at IIT Madras.

Now you are almost there to justify, how can you start a processor company from scratch, except a fundamental problem – who is going to educate the young about entire tool-chain, and who is going to provide tools for ASIC design for tape-out…Well…..continue reading, and we will get you a solution to that as well

Post-lunch, me and Anagha presented a unique paper, focusing on 2 main points – first, the power of open-source EDA tools, and its status on hierarchical front. Second, the power of technology mediated learning.

Anagha, who is with me and Prof. Madhusudhan in above pic presented a unique problem, currently seen in the growing RISC-V ecosystem, i.e. “where to start”, “who will educate” and “who will empower” the young student community, who are the future.

That’s where our technology mediated solution on video-cloud based learning, using opensource EDA tools, helps, and we are going to promote this a lot in coming days, so that, even the young people start dreaming about starting a processor company from scratch

Following this, Niraj, India head, Bluespec presented a talk on formal specification of RISC-V ISA, that describes the subtleties induced by requiring “universality”, “modularity” and “concurrency”

Finally, RISC-V workshop was concluded by Rick O’ Connor and Prof. Kamakoti. Rick pointed out one important opportunity, with which we started a blog i.e. “How can you and I start a processor company?” This blog (and RISC-V workshop) now has that answer. It just a matter of time and a bit of push you need from within (as I said earlier)

“The man who moves a mountain begins by carrying away small stones” – The movement has started in India

I would encourage you all to attend any RISC-V workshop happening in your region…Maybe we might meet-up, and you will witness the energy

All the best and happy learning….

Registration for Ethical RISC-V IoT Workshop

Welcome to Ethical RISC-V IoT Workshop

The “Ethical RISC-V IoT Workshop” at IIIT Bangalore, organized in collaboration with VSD, is a structured, educational competition aimed at exploring real-world challenges in IoT and embedded systems. Participants progress through three stages: building an application, injecting and managing faults, and enhancing application security. The event spans from May 9 to June 15, 2024, culminating in a showcase of top innovations and an award ceremony. This hands-on hackathon emphasizes learning, testing, and securing applications in a collaborative and competitive environment.

Rules :
  1. Only for Indian Student whose college is registered under VTU
  2. Only team of 2 members can Register
  3. Use only VSDSquadron Mini resources for product development
Awards :
  1. Prize money for final 10 Team
  2. 3 Winner team’s Product will be evaluated for Incubation
  3. 7 consolation prizes
  4. Completion Certificate to final round qualifier
  5. Chance to build a Proud Secured RISC-V Platform for India

Date for Registration : 9th May - 22nd May, 2024
Hackathon Inauguration : 23rd May 2024

VSDSquadron (Educational Board)

VSDSquadron, a cutting-edge development board based on the RISC-V architecture that is fully open-source. This board presents an exceptional opportunity for individuals to learn about RISC-V and VLSI chip design utilizing only open-source tools, starting from the RTL and extending all the way to the GDSII. The possibilities for learning and advancement with this technology are limitless.

Furthermore, the RISC-V chips on these boards should be open for VLSI chip design learning, allowing you to explore PNR, standard cells, and layout design. And guess what? vsdsquadron is the perfect solution for all your needs! With its comprehensive documentation and scalable labs, thousands of students can learn and grow together.

VSD HDP (Hardware Design Program) Duration-10 Week

With VSD Hardware Design Program (VSD-HDP),  you have the opportunity to push the boundaries of what exist in open source and establish the new benchmark for tomorrow.

It will leverage your degree in Electrical or Computer Engineering to work with

  • Programmable logic
  • Analog/ digital IP
  • RISC-V
  • Architecture & microprocessors
  • ASICs and SoCs on high-density digital or RF circuit cards
  • Gain hands-on knowledge during design validation and system integration.

Sounds exciting to just get started with expert mentors, doesn’t it? But we are looking for the next generation of learners, inventors, rebels, risk takers, and pioneers.

“Spend your summer working in the future !!”

Outcomes of VSD Online Research IP Design Internship Program

  1. Job opportunities in Semiconductor Industry
  2. Research work can be submitted to VLSI International journals
  3. Participate in Semiconductor International Conference with Internship Research Work
  4. Paper Publications in IEEE Conference and SIG groups
  5. Tape out opportunity and IP Royalty
  6. Interact with world class Semiconductor designer and researchers
  7. Academic professions where more research projects are encouraged.
  8. All the above research and publication work will help colleges and institutes to improve accreditation levels.

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VSD – Intelligent Assessment Technology (VSD-IAT)

VSD – Intelligent Assessment Technology (VSD-IAT) is expertly built training platform and is suited for designer requirements. Semiconductor companies understand the value of training automation and Engineer performance enhancement, and do not need to be convinced of the impact of a virtual platform for learning. VSD trainings are quick, relevant, and easy to access from any device at any time zone.

VSD Intern Webinars

VSD Interns made it happen !!

VSD is working towards creating innovative talent pool who are ready to develop design and products for the new tech world. VSD believes in “Learning by doing principle” , and always prepare the student to apply the knowledge learned in the workshops, webinars and courses. We always push our students to work on new designs, test it and work continuously till it becomes the best performing design. Any student who enrolls to VSD community starts working with small design and grows with us and develops a tapeout level design with complete honesty and dedication towards the Work !!

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VSDOpen Online Conference

Welcome to the World’s only online conference in Semiconductor Industry VSDOpen Conference. With enormous support and global presence of audience from different segments of industrial lobby and academia made a highly successful event. Evolution is change in the genetic makeup of a population over time, online conference is one kind evaluation everyone adapt soon. 

  • VSDOpen 2022 is an online conference to share open-source research with the community and promote  hardware design mostly done by the student community.
  • VSDOpen 2022 is based on the theme “How to lower the cost to learn, build, and tapeout chips ?”  , which will provide a platform to community to build stronger designs and strengthen the future of Chip design.
  • VSDOpen is envisioned to create a community based revolution in semiconductor hardware technology.
  • The open source attitude is required to bring out the talent and innovation from the community who are in remote part of world and have least access to the technologies.  And now Google support will help to bring the vision to execution by VSD team

VSD Online Course by Kunal Ghosh

VSD offers online course in complete spectrum of vlsi backend flow from RTL design, synthesis and Verification, SoC planning and design, Sign-off analysis, IP Design, CAD/EDA automation and basic UNIX/IT, Introduction to latest technology – RISC-V, Machine intelligence in EDA/CAD, VLSI Interview FAQ’s.

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