“And suddenly you know: It’s time to start something new and trust the magic of beginnings” Meister Eckhart….he was so right…
Though 2-day RISC-V workshop has come to an end at IIT Madras, trust the magic of beginnings. Not only, this workshop was a boost to RISC-V ecosystem, it was also a boost to Indian start-up ecosystem, where now, me and you, together can start a processor company, without much of legal hassles.
ISA is opensource, many RISC-V cpu cores are available at gitbub and free to download, and on top of that, if I say, we are on the path, where you can now implement your core using opensource EDA tools…Wowww….That’s a new exciting never-seen-before model in semi-conductor industry. All you need is a push from within and think like an “entrepreneur” – By the way, that’s how Amazon, Facebook, Google and even Apple had started-up….
Key highlights of Day 2 were Ashish Patra’s talk. He is Principal R&D engineer from Western Digital, and his talk focused to 2 important things – first was regarding current capabilities of Linux on RISC-V, which would serve a guide for developers to make design choices for prototyping and performance bench-marking. And second – it serves as a guide for new developers who are willing to start contributing towards RISC-V kernel port
Next, Muhammad Arsath from IIT Madras presented his evaluation work on data-leaks on SHAKTI C-Class, which is a RISC-V based microprocessor. Vinod and Gopinath from IIT Madras described more about “Risecreek” (test SoC around SHAKTI-C64). “Risecreek” has been taped out using Intel 22nm technology node. Luke wrapped up pre-lunch talk on SHAKTI M-Class Libre RISC-V SoC, that outlined plan on how to design and bring to market a mass-volume commercial System-on-Chip. These talks did show the energy and excitement behind India’s RISC-V SoC ecosystem.
To add to above, Paul George from IIT Madras presented Shakti Lockstep Verification Framework (SLSV) for dynamic verification and post-silicon validation. The good part – SLSV is completely open-source framework being developed at IIT Madras.
Now you are almost there to justify, how can you start a processor company from scratch, except a fundamental problem – who is going to educate the young about entire tool-chain, and who is going to provide tools for ASIC design for tape-out…Well…..continue reading, and we will get you a solution to that as well
Post-lunch, me and Anagha presented a unique paper, focusing on 2 main points – first, the power of open-source EDA tools, and its status on hierarchical front. Second, the power of technology mediated learning.
Anagha, who is with me and Prof. Madhusudhan in above pic presented a unique problem, currently seen in the growing RISC-V ecosystem, i.e. “where to start”, “who will educate” and “who will empower” the young student community, who are the future.
That’s where our technology mediated solution on video-cloud based learning, using opensource EDA tools, helps, and we are going to promote this a lot in coming days, so that, even the young people start dreaming about starting a processor company from scratch
Following this, Niraj, India head, Bluespec presented a talk on formal specification of RISC-V ISA, that describes the subtleties induced by requiring “universality”, “modularity” and “concurrency”
Finally, RISC-V workshop was concluded by Rick O’ Connor and Prof. Kamakoti. Rick pointed out one important opportunity, with which we started a blog i.e. “How can you and I start a processor company?” This blog (and RISC-V workshop) now has that answer. It just a matter of time and a bit of push you need from within (as I said earlier)
“The man who moves a mountain begins by carrying away small stones” – The movement has started in India
I would encourage you all to attend any RISC-V workshop happening in your region…Maybe we might meet-up, and you will witness the energy
All the best and happy learning….