Building India’s next generation of women chip designers
Every chip that powers our phones, cars and data centres starts with an engineer who designs it. For decades, the women who could become those engineers have been missing, especially women from economically weaker backgrounds.
The VLSI Design Engineer Program for Women in Semiconductors was created to change that.
A door that was always closed
Chip design is one of the most rewarding careers in technology. It’s also one of the hardest to get into. It needs expensive EDA tools, specialised mentors and hands-on lab experience that most colleges can’t offer.
For a talented woman from a low-income family, these barriers often end the journey before it begins. Her ability was never the problem. Access was.
This program removes that barrier. It’s fully funded through Marvell Technology’s CSR initiative, so selected candidates pay nothing. Selection is based on one thing only: merit, proven through hands-on work.
The response
When the program was inaugurated, all 450 registered women engineers attended. Not one seat was empty.
That number shows how many capable women across India have been waiting for a real way into semiconductors.
Mrs. Parnika Pavanram, Advisor for Workforce Development & CoE Ecosystem at SFAL, delivered the inaugural address. She led the Karnataka ESDM Policy and has long worked to bring women into tech, help them return after career breaks and develop talent from tier 2 and 3 cities.
The impact
For women: a path to a respected, well-paid and future-proof career in chip design.
For families: one engineer’s career can change a household’s financial future for good.
For communities: every woman who succeeds becomes proof that chip design is within reach for girls from small towns and modest backgrounds.
For the nation: a larger, more diverse design workforce for India’s semiconductor ambitions and the India Semiconductor Mission.
For the industry: job-ready engineers with real proof of work, and the fresh perspectives that diverse teams bring.
Program at a glance
- Exclusively for women B.E./B.Tech engineers from the EWS category
- ₹0 program fee for selected candidates
- 570 hours of in-person training at SFAL, Bengaluru
- Merit-based selection through a hands-on SKY130 physical verification lab using open-source EDA tools
- A curriculum that covers VLSI fundamentals, RTL & Verilog, processor and SoC design with RISC-V, the ASIC/FPGA/EDA flow, verification and design automation
- Daily hands-on labs on cloud-based EDA tools
- Every lab and project documented on GitHub, so each engineer graduates with a portfolio employers can see
- ESSCI certification (ELE/Q1201) on successful assessment
- Placement support with resume building, mock interviews and employer outreach, aiming to place at least 70% of the batch
The partners behind it
| Partner | Role |
| Marvell Technology | CSR Sponsor |
| VSD (VLSI System Design) | Training partner: screening, training, labs and placement support |
| SFAL | Program partner: Bengaluru venue and EDA tool access |
| ESSCI | Project monitoring, assessment and certification |
A bigger idea
This program is about more than one batch of engineers. It’s built on a simple belief: talent is everywhere, but opportunity is not.
When women have access to the right tools, mentors and proof-of-work training, they don’t just join the semiconductor industry. They help shape it.
The future of chip design is being built here, and she’s building it.
