The Complete VLSI Design Flow: From Specification to Silicon, Board and Product

A clear learning roadmap for freshers choosing their first VLSI program

VLSI is often introduced through disconnected terms: RTL, verification, synthesis, physical design, STA, DRC, LVS, tape-out and packaging. A fresher may recognise these words yet still struggle with the most important question:

How do all these activities connect to create a working semiconductor product?

The simplest answer is that chip development begins with a problem, moves through architecture and design, produces a manufacturable layout, and continues through fabrication, packaging, testing and board-level validation.

This article explains that journey from a 30,000-foot view. It also maps each stage to relevant programs on the VSD Learning Path, helping freshers choose a starting point that matches their interests.

1. Product specifications: What should the chip do?

Every chip begins with a problem—not with Verilog.

The specification defines the required functionality, performance, operating frequency, power budget, interfaces, memory, cost, area, reliability and intended application. For example, an edge-AI device may require sensor inputs, local inference, low power consumption and communication with an external host.

Input: A product or application requirement
Output: A measurable chip specification

VSD does not currently list a dedicated product-specification course. However, the application-to-processor relationship becomes clearer through the RISC-V based MYTH workshop and the Product-Based RISC-V Skilling Program.

The important lesson for a fresher is simple: RTL is an implementation of a specification. It is not the starting point of the product.

2. System architecture and microarchitecture: How will the chip work?

Architecture divides the specification into major subsystems such as processors, memories, buses, accelerators, peripherals, clocking, reset and analog interfaces.

Microarchitecture goes one level deeper. It defines how a processor or hardware block will implement that architecture through datapaths, control logic, pipelines, registers, ALUs and memory interfaces.

Input: Product specification
Output: Block diagram, interfaces and microarchitecture

For processor architecture, start with RISC-V based MYTH. It connects the RISC-V ISA to a basic and then pipelined CPU microarchitecture. Learners seeking deeper exposure to processor functionality, Verilog implementation, I/O and low-level C/assembly can continue with the Product-Based RISC-V Skilling Program.

3. RTL design and IP integration: Converting architecture into hardware logic

Register-transfer level, or RTL, describes how data moves between registers and how combinational and sequential logic transforms it. Verilog or another hardware description language is used to implement counters, controllers, interfaces, processors and other digital blocks.

An SoC is rarely written entirely from scratch. Designers integrate reusable IP such as processor cores, memories, GPIO, UART, SPI, timers, PLLs and analog blocks. Every IP must have clearly defined clocks, resets, interfaces and timing expectations.

Input: Architecture and block-level specifications
Output: Synthesizable RTL and an integrated SoC design

A learner with little or no Verilog experience should begin with Master RTL Design and Synthesis. It covers RTL coding, simulation, testbenches, debugging and Yosys synthesis using SKY130 standard cells.

After learning basic RTL, RISC-V based MYTH provides a meaningful processor project, while the VSD Hardware Design Program expands the journey towards a complete RTL-to-GDSII implementation.

4. Functional verification: Does the RTL behave correctly?

Before implementation, the RTL must be checked against the specification. Verification teams build testbenches, generate stimulus, inspect waveforms, write assertions and test normal, corner and error conditions.

Verification is not a single box that is completed once. It begins with individual blocks, continues at subsystem and SoC level, and reappears after synthesis and physical design through gate-level and post-layout checks.

Input: RTL and verification plan
Output: Functionally validated RTL, test results and bug reports

Master RTL Design and Synthesis introduces simulation, waveform debugging and testbench development. RISC-V based MYTH applies basic verification to processor design. The VSD Hardware Design Program adds pre-synthesis, post-synthesis and gate-level comparisons.

Freshers should note that the current VSD product page does not show a dedicated UVM, formal-verification or assertion-based verification program. These are natural advanced topics after mastering RTL and basic testbench development.

5. FPGA prototyping: Testing the design before manufacturing silicon

Verified RTL can be implemented on an FPGA. The FPGA flow performs synthesis, mapping, placement, routing and bitstream generation. The bitstream configures programmable logic so the design can run on real hardware.

FPGA prototyping allows designers to test interfaces, firmware and system behaviour before committing to the cost and time of ASIC fabrication. Problems discovered on the board can feed back into the architecture or RTL.

Input: Verified RTL
Output: FPGA bitstream and hardware validation results

The FPGA Fabric Design and Architecture Workshop explains LUTs, CLBs, switch boxes, routing and FPGA fabric construction. Learners ready to build processor peripherals and reusable IP can continue with the RISC-V FPGA IP Internship.

This is an optional branch in an ASIC project, but it is extremely valuable for processor, embedded-system and product-oriented designs.

6. Logic synthesis and DFT: Converting RTL into gates

Logic synthesis converts RTL into a gate-level netlist using standard cells from a technology library. The synthesis tool optimises the design for timing, power and area while respecting design constraints.

Design for test, or DFT, adds structures such as scan chains and test access logic so manufacturing defects can be detected after fabrication.

Input: Verified RTL, timing constraints and standard-cell libraries
Output: Optimised gate-level netlist and test-ready design

Master RTL Design and Synthesis is the most direct beginner program for understanding RTL-to-gate conversion. The VSD Hardware Design Program covers synthesis, constraints, optimisation and post-synthesis analysis. The SoC Design and Implementation Program uses Synopsys Design Compiler for industry-tool exposure.

The current VSD catalogue does not list a dedicated DFT/ATPG program, so learners should treat DFT as a specialised continuation after synthesis fundamentals.

7. Physical design: Giving the netlist a physical shape

A gate-level netlist describes connectivity but does not specify where cells and wires will physically exist on silicon. Physical design converts the netlist into a manufacturable layout.

The principal stages are:

Floorplanning: Define die/core size, I/O locations, macros and power distribution.
Placement: Position standard cells while considering timing, congestion and power.
Clock Tree Synthesis: Distribute the clock while controlling skew and insertion delay.
Routing: Connect all signal, clock and power nets using available metal layers.
Optimisation: Fix timing, congestion, transition, capacitance and design-rule problems.

Input: Synthesised netlist, constraints, libraries and PDK
Output: Placed-and-routed physical database

The strongest entry point is Digital VLSI SoC Design and Planning, which introduces floorplanning, standard cells, timing and the OpenLANE RTL-to-GDSII flow.

For deeper project work, learners can choose the VSD Hardware Design Program, the VSDSquadron RTL-to-GDS Program, or the SoC Design and Implementation Program using Synopsys tools.

Although Digital VLSI SoC Design and Planning is listed as a starter course, it technically maps to the physical-design and sign-off portion of the chip flow. A complete beginner will understand it better after gaining basic RTL and synthesis knowledge.

8. Sign-off analysis: Will the chip meet timing, power and reliability targets?

A routed layout is not ready for manufacturing merely because every connection exists. Engineers must prove that the design works across process, voltage and temperature conditions.

Sign-off activities include:

Static timing analysis for setup, hold and clock checks
Parasitic extraction for interconnect resistance and capacitance
Signal-integrity and crosstalk analysis
Power analysis
IR-drop and electromigration analysis
Timing closure across operating corners

Input: Routed layout, parasitics and timing libraries
Output: Sign-off reports and a timing/power-clean design

Digital VLSI SoC Design and Planning introduces timing analysis using OpenSTA. The VSD Hardware Design Program performs STA after synthesis, placement, CTS and routing. For commercial-tool exposure, the SoC Design and Implementation Program uses PrimeTime and StarRC.

Timing closure is iterative. Violations may require changes to constraints, synthesis, placement, clock trees or routing.

9. Physical verification: Is the layout manufacturable and equivalent?

Physical verification checks whether the final layout can be manufactured and whether it still represents the intended circuit.

Important checks include:

DRC: Does the geometry follow foundry manufacturing rules?
LVS: Does the extracted layout match the intended schematic or netlist?
ERC: Are electrical connectivity and device usage valid?
Antenna checks: Could fabrication-induced charge damage gates?
Density and fill: Is metal distribution suitable for manufacturing?
Extraction: What parasitic resistance and capacitance were introduced by layout?

Input: Final layout and foundry rule decks
Output: DRC/LVS/ERC-clean, tape-out-ready GDSII

The most direct program is Physical Verification for Tapeout Readiness using SKY130. It covers DRC, LVS, extraction, antenna, density, hierarchy, macros and GDS sign-off using open-source tools. The SoC Design and Implementation Program also introduces physical verification through Synopsys IC Validator.

10. GDSII tape-out and fabrication: Sending the design to a foundry

After sign-off, the final GDSII database and supporting information are submitted for tape-out. The foundry uses this data to generate masks and fabricate wafers through repeated deposition, lithography, etching, implantation and metallisation processes.

Input: Signed-off GDSII and tape-out package
Output: Fabricated wafers containing the designed dies

The VSD Tapeout initiatives provide the closest connection to this stage. Physical Verification and RTL-to-GDSII programs prepare learners for tape-out, but semiconductor fabrication itself is a specialised foundry discipline and is not currently presented as a standalone VSD course.

11. Packaging and testing: Turning a die into a usable component

Fabricated dies must be separated from the wafer, assembled into packages, connected to package pins or bumps, protected and tested.

Packaging affects electrical performance, thermal behaviour, mechanical reliability, signal integrity, power delivery and system cost. Modern options include wire-bond packages, flip-chip, wafer-level packaging, chiplets and 2.5D/3D integration.

Input: Fabricated and tested dies
Output: Packaged semiconductor devices ready for system use

The Packaging Fundamentals of Design and Testing workshop covers package selection, assembly, thermal simulation, reliability, testing, wire bonding, flip-chip and advanced packaging concepts.

12. Silicon and board bring-up: Does the real chip work?

After packaging, engineers place the device on a PCB and power it on. They verify clocks, reset, power rails, JTAG, memories, peripherals, firmware and external interfaces.

This stage reveals problems that simulation may not have exposed. The team compares real measurements against pre-silicon expectations, diagnoses failures and qualifies the system across operating conditions.

Input: Packaged chip, PCB, firmware and test plan
Output: Working silicon, board-level evidence and characterised performance

The RISC-V Embedded Firmware Internship and VSDSquadron hardware platform help learners understand the relationship between processors, firmware, interfaces and physical hardware.

13. Product validation: From a working chip to a useful solution

A successful chip is not automatically a successful product. The final system must solve its target problem reliably, repeatedly and within power, performance and cost limits.

Product validation may include application workloads, AI-model deployment, sensor testing, communications, environmental testing, security, firmware updates and long-duration reliability checks.

Input: Working silicon and board
Output: A validated electronic product or demonstrator

Learners interested in connecting RISC-V hardware to real AI workloads can explore the RISC-V EdgeAI Workshop and the RISC-V Edge AI Internship.

The parallel analog and mixed-signal IP flow

Digital RTL is only one part of a modern SoC. Chips also require transistor-level blocks such as PLLs, bandgaps, ADCs, DACs, SRAMs, I/O cells and power-management circuits.

The custom-IP flow generally follows:

Circuit specification → schematic → SPICE simulation → device sizing → PVT analysis → custom layout → extraction → post-layout simulation → IP sign-off → SoC integration

Start with CMOS Circuit Design and SPICE Simulation using SKY130 to understand MOSFET behaviour, CMOS inverters, noise margins, delay, power and PVT variation.

Continue with Bandgap IP Design using SKY130 to design and characterise a real analog reference block. Learners interested in advanced transistor technology can then explore FinFET Circuit Design and Characterization.

The completed analog IP supplies behavioural models and interfaces for SoC verification, timing/power models for design tools, and physical abstracts or GDS for physical integration.

Which VSD program should a fresher start with?

There is no single first course for everyone. The correct starting point depends on the role you want to explore.

Your interest	Recommended first program	Suggested progression
Digital RTL or ASIC front-end	Master RTL Design and Synthesis	Master RTL → RISC-V MYTH → VSD-HDP
CPU architecture or RISC-V	RISC-V based MYTH	MYTH → Product-Based RISC-V → FPGA/IP project
FPGA and digital IP	Master RTL or RISC-V MYTH	FPGA Fabric → RISC-V FPGA IP Internship
Physical design	Master RTL if Verilog is new; otherwise Digital VLSI SoC	Digital VLSI SoC → Physical Verification → VSD-HDP/VSDSquadron
Analog or mixed-signal design	CMOS Circuit Design and SPICE Simulation	CMOS → Bandgap IP → Physical Verification → Mixed-Signal IP project
Semiconductor packaging	Packaging Fundamentals of Design and Testing	Packaging → advanced package/thermal/reliability projects
Embedded systems or hardware products	RISC-V MYTH or Embedded Firmware Internship	Firmware → FPGA/board validation → Edge AI/product project

Four clear learning routes

Final perspective

The semiconductor journey does not end when RTL simulates correctly. It does not end when synthesis produces a netlist, when physical design produces GDSII, or even when a chip is fabricated.

A complete electronic-product journey is:

Problem → Specification → Architecture → RTL/IP → Verification → Prototype → Synthesis → Physical Design → Sign-off → Physical Verification → Tape-out → Fabrication → Packaging and Test → Board Bring-up → Product Validation

Freshers do not need to master every stage immediately. They need to understand the complete map, select one entry point and build evidence through labs, reports, GitHub repositories, hardware demonstrations and progressively larger projects.

That is how isolated VLSI topics become a coherent semiconductor career journey.

Explore the complete collection of courses, workshops, boards and internships on the VSD Products and Learning Path page.