Welcome to the World’s only online conference in Semiconductor Industry VSDOpen Conference 2019. With enormous support and global presence of audience from different segments of industrial lobby and academia made VSDOpen 2018 a highly successful event. Evolution is change in the genetic makeup of a population over time, online conference is one kind evaluation everyone adapt soon. 

  • VSDOpen 2019, we are bringing you more interesting work done in RISC-V domain and Open Source EDA tools.  
  • Industry and Academic research talks about the chip designed and developed using RISC-V ISA from IIT Madras India and SweRV from Western Digital.
  • First of its kind, Virtual Booth to Demonstrate the working RISC-V Chip and Board developed in complete Open source domain.

VSDOpen 2019 is free to attend! Anyhow, you must Register, so that we can plan better.

Date & Venue: LIVE ONLINE

Distinguished Conference Keynote Speakers

Keynote Speakers Profile

Biodata:Dr. Andrew Kahng is world-renowned for his contributions to design automation methods for implementing complex integrated-circuit systems in semiconductors.Dr. Kahng developed integrated-circuit physical design methods which maximise the system performance achieved using the most advanced semiconductor technologies.Dr. Kahng pioneered many foundations of a new methodology called Design for Manufacturability (DFM) for semiconductor products.Dr. Kahng for nearly two decades played a key role in the creation of the International Technology Roadmap for Semiconductors, setting out future directions for semiconductor and design technology research worldwide.Professor Kahng is the author of 3 books and 400+ journal and conference papers. He holds 34 issued U. S. patents.Professor Kahng co-founded Blaze DFM Inc. and served as CTO, an EDA software company that delivered new cost and yield optimisations at the IC design-manufacturing interface. The Blaze DFM core technology is responsible for substantial leakage power and total power reductions in such high-volume products as AMD/ATI Radeon graphics processor chips, and starting in ~2008 was embodied in the TSMC Power Trim Service that enables low integrated-circuit power consumption and green products. Dr. Kahng is Principal Investigator of IDEA Program of DARPA.

Biodata:Calista Redmond is the CEO of the RISC-V Foundation with a mission to expand and engage RISC-V stakeholders, compel industry adoption, and increase visibility and opportunity for RISC-V within and beyond the Foundation. Prior to the RISC-V Foundation, Calista held a variety of roles at IBM, including Vice President of IBM Z Ecosystem where she led strategic relationships across software vendors, system integrators, business partners, developer communities, and broader engagement across the industry. Focus areas included execution of commercialization strategies, technical and business support for partners, and matchmaker to opportunities across the IBM Z and LinuxOne community. Calista’s background includes building and leading strategic business models within IBM’s Systems Group through open source initiatives including OpenPOWER, OpenDaylight, and Open Mainframe Project. For OpenPOWER, Calista was a leader in drafting the strategy, cultivating the foundation of partners, and nurturing strategic relationships to grow the org from zero to 300+ members. While at IBM, she also drove numerous acquisition and divestiture missions, and several strategic alliances. Prior to IBM, she was an entrepreneur in four successful start-ups in the IT industry. Calista holds degrees from the University of Michigan and Northwestern University.

Biodata:Daniel has worked in Silicon Valley for the past 35 years with semiconductor manufacturers, electronic design automation software, and semiconductor intellectual property companies. Daniel Nenni is the founder of SemiWiki.com (an open forum for semiconductor professionals) and the co-author and publisher of “Fabless: The Transformation of the Semiconductor Industry”, “Mobile Unleashed: The Origin and Evolution of ARM Processors in our Devices”, “Prototypical: The Emergence of Prototyping for SoC Design”, “Custom SoCs for Iot: The Emergence of Custom Silicon for IoT Devices” and “SoC Emulation Bursting into its Prime”. Daniel is an internationally recognised business development professional for companies involved with the fabless semiconductor ecosystem.

Invited Talks by Industry and Academia Expertise

Invited Speaker Profile

Biodata:Dr.V.Kamakoti received the M.S. degree and the Ph.D. degree in computer science and engineering from IIT Madras, Chennai, India.,He is currently a Professor with the Department of Computer Science and Engineering and Associate Dean at ICSR,IIT Madras. He has more than 15 years of experience in computer systems development and specializes in the area of computer architecture, CAD for VLSI, and high performance computing. Dr. Kamakoti took SHAKTI processor initiative which aim to break the barrier between Academia and Industry by providing open-source Processor and SoC designs. He has authored a number of research papers that have been published in various international journals and in the PROCEEDINGS of many scientific conferences. Dr.Kamakoti also has interest in writing literature and has published Ganiporiyum Adipadiyum, a book in Tamil released in 1992. Dr.Kamakoti was research guide for 10 PhD students who have already graduated and 9 are ongoing. The paper entitled A Parallel Genetic Approach, using artificial neural networks, to temporal partitioning and synthesis for reconfigurable architectures won the Excellent Presentation Award at the Third Inter- national Symposium on Advanced Intelligent Systems (ISIS) held at Tsukuba, Japan, 2002. Dr.Kamakoti received DRDO Academic Excellence Award instituted by DRDO in recognition of the contribution from Academicians to various programs of DRDO. Recently, Dr.Kamakoti was awarded  Techno Visionary Award, which is a lifetime achievement award given to an Indian academician, who made significant contributions to the field of Electronics and Semiconductor through research and development.

Biodata:Ted Marena is responsible for accelerating the build out of the RISC-V ecosystem and promoting machine learning solutions. He has over 25 years’ experience in electronics and excels at business development, marketing and revenue growth. Marena was appointed the interim director of CHIPS Alliance, an organization focused on developing open source CPUs, peripherals and complex IP blocks for silicon. Marena previously worked at Microsemi where he was awarded the Rock Star status for marketing the SoC FPGA product lines. He was elected Marketing Chair for the RISC-V organization in 2016.  Marena was awarded US patent 9009379 in 2015. He earned Innovator of the Year in 2014 when he worked for Lattice Semiconductor.  Marena has defined, created and executed unique marketing solutions for data center, consumer, machine learning, industrial IoT and automotive applications. Marena started working as a design engineer, field application engineer and a sales manager before he moved to marketing and business development.  His understanding of the complete electronics design cycle has earned him a reputation as an expert marketer in the electronics industry.Marena holds a Bachelor of Science in electrical engineering Magna Cum Laude from the University of Connecticut and a MBA from Bentley University’s Elkin B. McCallum Graduate School of Business

Conference Chair

Call for paper

Scope of Paper: We are accepting papers from authors around the world who have used open-source EDA tools to implement their RISC-V or similar designs. If you’ve designed, worked on or even just used open source IP cores and/or management systems, verification IP, build flows, SoCs, simulators, synthesis tools, FPGA and ASIC implementation tools under below mentioned topics.

  1. Front-end open-source EDA tool flows for IC design and verification
  2. Clock tree synthesis and optimization of digital IC  for best Performance
  3. Floorplanning of digital IC for best area
  4. Place and Route of digital IC  for best PPA
  5. RISC-V based SoC development using RISC-V software stack

LIVE Open Source HW Demo Booth

Pulp based HW Demo

  • The Parallel Ultra Low Power (PULP) project is the flagship project of
    research groups at ETH Zurich and University of Bologna led by Prof.
    Luca Benini
  • The PULP project has released a large collection of RISC-V based
    systems from simple micro-controllers to multi-cluster systems using a
    permissive open source license
  • PULP systems are designed using System Verilog and parts of the
    project have found wide-spread use in both industry and academia
  • The PULP project started as a research project in academia, but
    industry has shown great support for it, Greenwaves Technologies and
    Open-isa.org have released development boards based on PULP technology
    and recently the OpenHW group with 13 founding members has announced
    that it will support several cores from the PULP project as part of
    their Core-V project.

The Raven chip: First-time silicon success with qflow and efabless

VSDOpen 2018 Reviews & Feedback

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“Good conference but if we get the recording or ppt which presented it would be very helpful.”

Omkar reddy

“Fantastic..!!”

Chirag Kasliwal

“Hello VSD team!It was really a great experience getting to know about open source hardware and tl verilog. Also got an opportunity to meet some great and amazing people in the industry . I attended this conference from Oman. I had to wake up at 6am . But I don’t regret it at all now. Apart from occasional disturbances the audio and video clarity was all good. Kudos to Kunal and Anagha and all the VSD team! They executed it perfectly. Eagerly waiting for more conferences like this in future.”

EWEL DOMINIC SAVIO ANTONY