Selective Non-Default Rules Based Clock Tree Synthesis using open-source EDA
Hey There – Think about it…!! Problem Statement – For hierarchical designs ~500k instance count, participants are expected to develop code which will modify existing […]
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Default-Rules Based Clock Tree Synthesis in open-source EDA
For hierarchical designs ~500k instance count, participants are expected to develop code which will build clock tree for a design which has close to ~50k sequential flip-flops using default routing rules
How about pre-route and power-grid generation in opensource EDA?
Hey There – Think about it!! Today’s version of open-source EDA tools, work very well for hierarchical designs sub-25k instance count. For hierarchical designs ~500k […]
Let’s re-think open-source EDA – core and die
Hey There – Think about it!!! Today’s version of open-source EDA tools, work very well for hierarchical designs sub-25k instance count. For hierarchical designs ~500k […]
History etched with VSDOpen2018 – First VLSI online conference….
Hi “Pictures speak it all” Finally, we all did it – VSDOpen – first ever online VLSI conference. Very close to a real one – […]
