The horrible std cell ever designed by me….

Power rail discontinuity – We would like to have continuous power rail.N- and P-diffusion discontinuity – We would like to have continuous diffusion. For my Physical design friends, remember, we add “FILLER” cells at the end of routing, and you always wondered why we are doing so.Small substrate contacts – Except for inverter, all substrate contacts are single width, which will create high resistance path for current, thus increasing “Clk-to-Q” delay.Hanging metal1 – If you see for the NAND gate outputs, there is lot of hanging metal1.

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Latch timing – Beg, borrow or steal !!

Sounds crude … This is how it functions. Well, in my opinion, it’s not as crude as it sounds, but a very smart way to achieve high performance in some critical cases. Let’s start with what it looks like. A latch is nothing but a part of a flipflop. In […]

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