An overview of Design Automation Conference (DAC) 2018

That’s exactly what happened in DAC2018 at Moscone Center, San Francisco. I was invited for a talk in DAC summer school, on my work “vsdflow” which is also one of the main topics of discussion in my “TCL programming” course on Udemy. I would say, the entire DAC was a journey of events, exchange of ideas between brightest minds of the world.

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VSDSYNTH – An unique UI for synthesis and pre-layout timing

online VLSI courses using open-source tools, VSDSYNTH, our new product (currently in beta testing) is unique UI that will take in inputs in form of RTL netlist and read standard SDC format constraints. The UI will generate synthesized netlist and pre-layout timing reports, hereby giving you first hand information on the quality of your RTL design

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Hey is your laptop ready to design a chip??

Hello Or atleast analyze full chip timing? No…..Then get it ready soon… We will soon be launching course on static timing analysis – part 2 and physical design – part 2 that will rely heavily on open source EDA tools, which might be a bit difficult to be done in […]

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