An overview of Design Automation Conference (DAC) 2018

That’s exactly what happened in DAC2018 at Moscone Center, San Francisco. I was invited for a talk in DAC summer school, on my work “vsdflow” which is also one of the main topics of discussion in my “TCL programming” course on Udemy. I would say, the entire DAC was a journey of events, exchange of ideas between brightest minds of the world.

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eFabless is back…with synth/PD/DRC/LVS…and a working CHIP

A working chip is all using opensource EDA tools (no more license fee). Of course, its taped-out in 180nm technology. But who knows, this might be just the beginning. Upcoming blogs will talk more about the commercial angle of this. Let’s see how it is going to benefit student/professionals/innovators community

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VSDSYNTH – An unique UI for synthesis and pre-layout timing

online VLSI courses using open-source tools, VSDSYNTH, our new product (currently in beta testing) is unique UI that will take in inputs in form of RTL netlist and read standard SDC format constraints. The UI will generate synthesized netlist and pre-layout timing reports, hereby giving you first hand information on the quality of your RTL design

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