In this 8-week internship I spent the first week on researching existing work and making design decisions for the PLL components namely – Phase Frequency Detector, Charge Pump, Voltage Controlled Oscillator and Frequency Divider. I also looked into linking of the Sky130nm PDK with SPICE for the circuit implementation.
Since then, we have promoted courses using a lot of open-source EDA tools like Opentimer for STA, qflow for Physical design, TL-verilog for pipelining, Yosys for Synthesis, Proton for EDA and many more. Not only that, we have organized an online conference (as you might be aware) and here’s the link with details:
Hello And you thought we are done with CPPR… No … not yet … We haven’t done the “Hold” analysis yet. Its simple, but its […]
Hello It’s been 5 days since my last post (and that was intentional). I wanted to go slow on this topic, as this is an […]